Reduced size semiconductor package with stacked dies

• US 6,927,478 B2
• Filed: 01/11/2002
• Issued: 08/09/2005
• Est. Priority Date: 01/15/2001
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Paek, Jong Sik
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Lewis, Monica
• Application Number:
  US10/043,946
• Publication Number:
  US 20020093087A1
• Time in Patent Office: 1,306 Days
• Field of Search: 257/666, 257/676, 257/678, 257/734, 257/777, 257/686, 257/778, 257/707
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package comprising a plurality of leads. Each of the leads defines opposed first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface. The first surface is oriented between the second and third surfaces. The semiconductor package further comprises first and second semiconductor dies which each define opposed first and second surfaces. Disposed on the first surface of the first semiconductor die are a plurality of bond pads, with bond pads also being disposed on the second surface of the semiconductor die. The first surface of the first semiconductor die is attached to the second surface of each of the leads, with the first surface of the second semiconductor die being attached to the second surface of the first semiconductor die. A plurality of conductive connectors or wires electrically connect the bond pads of the first and second semiconductor dies to respective ones of the leads. An encapsulating portion is applied to and at least partially encapsulates the leads, the first and second semiconductor dies, and the conductive connectors.

Claims

1. A semiconductor package comprising:

a plurality of leads, each of the leads defining;

a first surface;

a second surface disposed in opposed relation to the first surface; and

a third surface disposed in opposed relation to the second surface, the first surface being oriented between the second and third surfaces;

a first semiconductor die defining opposed first and second surfaces and including a plurality of bond pads disposed on the first surface thereof, portions of the first surface of the first semiconductor die being directly attached to the second surface of each of the leads such that at least some of the bond pads of the first semiconductor die are located between and laterally adjacent to a respective pair of the leads so that the bond pads of the first semiconductor die do not contact the second surface of any one of the leads;

a second semiconductor die defining opposed first and second surfaces and including a plurality of bond pads disposed on the second surface thereof, the first surface of the second semiconductor die being attached to the second surface of the first semiconductor die;

a plurality of conductive connectors electrically connecting the bond pads of the first and second semiconductor dies to respective ones of the leads; and

an encapsulating portion applied to and at least partially encapsulating the leads, the first and second semiconductor dies, and the conductive connectors.

2. The semiconductor package of claim 1 wherein the conductive connectors comprise conductive wires.

3. The semiconductor package of claim 1 wherein:

the conductive connectors comprise first and second conductive wires;

the bond pads of the first semiconductor die are electrically connected to respective ones of the first surfaces of the leads by the first conductive wires; and

the bond pads of the second semiconductor die are electrically connected to respective ones of the second surfaces of the leads by the second conductive wires.

4. The semiconductor package of claim 1 further comprising:

a die paddle defining opposed top and bottom surfaces, the leads being disposed about the die paddle;

the first surface of the first semiconductor die further being attached to the top surface of the die paddle.

5. The semiconductor package of claim 4 wherein:

the first surface of the first semiconductor die is attached to the second surface of each of the leads and to the top surface of the die paddle by a first bonding means; and

the first surface of the second semiconductor die is attached to the second surface of the first semiconductor die by a second bonding means.

6. The semiconductor package of claim 4 wherein:

the die paddle is formed to have a die paddle thickness;

each of the leads is formed to have a lead thickness between the second and third surfaces thereof; and

the die paddle thickness is substantially equal to the lead thickness.

7. The semiconductor package of claim 4 wherein the encapsulating portion is applied to the die paddle such that the bottom surface of the die paddle is exposed within the encapsulating portion.

8. The semiconductor package of claim 7 wherein the encapsulating portion is applied to the leads such that the third surface of each of the leads is exposed within the encapsulating portion.

9. The semiconductor package of claim 1 wherein the encapsulating portion is applied to the leads such that the third surface of each of the leads is exposed within the encapsulating portion.

10. The semiconductor package of claim 1 wherein:

the first semiconductor die defines a peripheral edge; and

the conductive connectors electrically connecting the bond pads of the first semiconductor die to the leads are oriented inwardly relative to the peripheral edge of the first semiconductor die.

11. A semiconductor package comprising:

a plurality of leads;

a first semiconductor die including a plurality of bond pads disposed thereon, the first semiconductor die being directly attached to each of the leads such that at least some of the bond pads of the first semiconductor die are located between and laterally adjacent to a respective pair of the leads so that the bond pads of the first semiconductor die do not contact any of the leads;

a second semiconductor die including a plurality of bond pads disposed thereon, the second semiconductor die being attached to the first semiconductor die;

means for electrically connecting the bond pads of the first and second semiconductor dies to respective ones of the leads; and

an encapsulating portion applied to and at least partially encapsulating the leads, the first and second semiconductor dies, and the electrical connection means.

12. The semiconductor package of claim 11 wherein the electrical connection means comprises conductive wires.

13. The semiconductor package of claim 12 wherein:

each of the leads defines opposed first and second surfaces and a third surface which is opposed to the second surface, the first surface being oriented between the second and third surfaces;

the bond pads of the first semiconductor die are electrically connected to respective ones of the first surfaces of the leads by first conductive wires; and

the bond pads of the second semiconductor die are electrically connected to respective ones of the second surfaces of the leads by second conductive wires.

14. The semiconductor package of claim 13 wherein the encapsulating portion is applied to the leads such that the third surface of each of the leads is exposed within the encapsulating portion.

15. The semiconductor package of claim 11 further comprising:

a die paddle, the leads being disposed about the die paddle;

the first semiconductor die being attached to the die paddle.

16. The semiconductor package of claim 15 wherein:

the die paddle defines opposed top and bottom surfaces, with the first semiconductor die being attached to the top surface of the die paddle; and

the encapsulating portion is applied to the die paddle such that the bottom surface of the die paddle is exposed within the encapsulating portion.