Method and system for wafer and device level testing of an integrated circuit
First Claim
1. A tester for testing memory dice on a wafer, said tester comprising:
- a wafer probe card having connections for at least one device under test that comprises a double data rate (DDR) memory die on a wafer, wherein the connections of the wafer probe card present an impedance selected to emulate a characteristic impedance of an end-use environment for a packaged device containing the memory die; and
tester logic, coupled to the wafer probe card, that communicates test data with the device under test via the wafer probe card.
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Abstract
A tester comprises test logic and a connector for at least one device under test. The connector, which may comprise a wafer probe for dice on a wafer or a test fixture or either packaged integrated circuit devices or circuit board modules, has connections for the device under test that present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test. For example, in an embodiment in which the device under test comprises DDR memory and the end-use environment is a DDR memory module, the characteristic impedance is approximately 60 ohms. Because this accurate simulation is available even for dice on a wafer, the needless expense associated with packaging defective dies and assembling defective dies into modules can be avoided.
31 Citations
59 Claims
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1. A tester for testing memory dice on a wafer, said tester comprising:
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a wafer probe card having connections for at least one device under test that comprises a double data rate (DDR) memory die on a wafer, wherein the connections of the wafer probe card present an impedance selected to emulate a characteristic impedance of an end-use environment for a packaged device containing the memory die; and
tester logic, coupled to the wafer probe card, that communicates test data with the device under test via the wafer probe card. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A tester for packaged integrated circuit memory devices, said tester comprising:
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a test fixture having connections for at least one device under test that comprises a packaged integrated circuit double data rate (DDR) memory device, wherein the connections of the test fixture present an impedance selected to emulate a characteristic impedance of an end-use environment for the at least one device under test; and
tester logic, coupled to the test fixture, that communicates test data with the packaged memory device via the test fixture. - View Dependent Claims (22, 23, 24, 25, 26, 27, 33, 34, 35, 36, 37, 38, 39)
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- 28. The tester of claim 28, wherein during a WRITE operation, the one or more delay elements delay the at least one timing signal received by the at least one device under test relative to write data.
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40. A tester for memory modules, said tester comprising:
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a test fixture having connections for at least one device under test that comprises a double data rate (DDR) memory module, wherein the connections of the test fixture present an impedance selected to emulate a characteristic impedance of an end-use environment for the memory module; and
tester logic, coupled to the test fixture, that communicates test data with the at least one device under test via the test fixture. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
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57. A memory tester, comprising:
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a connector having connections for a double data rate (DDR) memory device under test that is one of the set of a memory die on a wafer, a packaged integrated circuit memory device and a memory module, wherein the connections of the connector present an impedance selected to emulate a characteristic impedance of an end-use environment for the device under test; and
tester logic, coupled to the connector, that communicates test data with the device under test. - View Dependent Claims (58)
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59. A method of testing an integrated circuit device, said method comprising:
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connecting to connections of a connector a memory device under test that is one of a double data rate (DDR) packaged integrated circuit memory device, a DDR memory die on a wafer, and a memory module, wherein the connections present an impedance selected to emulate a characteristic impedance of an end-use environment for the device under test; and
coupling test logic to the connector;
communicating test data between the device under test and the test logic via the connector to test the device under test.
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Specification