×

Low voltage differential to single-ended converter

  • US 6,927,606 B2
  • Filed: 10/07/2002
  • Issued: 08/09/2005
  • Est. Priority Date: 04/16/2001
  • Status: Expired due to Term
First Claim
Patent Images

1. A complementary metal-oxide-semiconductor circuit comprising:

  • a first circuit implemented in current-controlled CMOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;

    a differential signal to single-ended signal converter coupled to the first circuit, the converter including a differential stage with resistor loads and a dynamically adjusted tail current and configured to convert the differential signal from the first circuit to a single-ended CMOS logic signal; and

    a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in CMOS logic wherein substantially zero static current is dissipated, wherein the differential signal to single-ended signal converter further comprises;

    a differential pair of input NMOS transistors each coupled to a logic high node via a respective load resistor; and

    a current source NMOS transistor coupled between the differential pair of input NMOS transistors and a logic low node, and having a gate coupled to a drain terminal of one of the differential pair of input NMOS transistors.

View all claims
  • 5 Assignments
Timeline View
Assignment View
    ×
    ×