Low voltage differential to single-ended converter
First Claim
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1. A complementary metal-oxide-semiconductor circuit comprising:
- a first circuit implemented in current-controlled CMOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;
a differential signal to single-ended signal converter coupled to the first circuit, the converter including a differential stage with resistor loads and a dynamically adjusted tail current and configured to convert the differential signal from the first circuit to a single-ended CMOS logic signal; and
a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in CMOS logic wherein substantially zero static current is dissipated, wherein the differential signal to single-ended signal converter further comprises;
a differential pair of input NMOS transistors each coupled to a logic high node via a respective load resistor; and
a current source NMOS transistor coupled between the differential pair of input NMOS transistors and a logic low node, and having a gate coupled to a drain terminal of one of the differential pair of input NMOS transistors.
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Abstract
Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion process. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using a differential pair of NMOS transistors with resistors as load devices and an NMOS current source transistor that provides dynamically adjusted tail current.
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Citations
13 Claims
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1. A complementary metal-oxide-semiconductor circuit comprising:
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a first circuit implemented in current-controlled CMOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;
a differential signal to single-ended signal converter coupled to the first circuit, the converter including a differential stage with resistor loads and a dynamically adjusted tail current and configured to convert the differential signal from the first circuit to a single-ended CMOS logic signal; and
a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in CMOS logic wherein substantially zero static current is dissipated, wherein the differential signal to single-ended signal converter further comprises;
a differential pair of input NMOS transistors each coupled to a logic high node via a respective load resistor; and
a current source NMOS transistor coupled between the differential pair of input NMOS transistors and a logic low node, and having a gate coupled to a drain terminal of one of the differential pair of input NMOS transistors.
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2. A complementary metal-oxide-semiconductor circuit comprising:
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a first circuit implemented in current-controlled CMOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;
a differential signal to single-ended signal converter coupled to the first circuit, the converter including a differential stage with resistor loads and a dynamically adjusted tail current and configured to convert the differential signal from the first circuit to a single-ended CMOS logic signal; and
a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in CMOS logic wherein substantially zero static current is dissipated, wherein the differential signal to single-ended signal converter comprises;
a first NMOS transistor having a gate terminal coupled to receive a first half of a differential logic signal from a first branch of the first circuit, a source terminal, and a drain terminal;
a second NMOS transistor having a gate terminal coupled to receive a second half of a differential logic signal from a second branch of the first circuit, a source terminal coupled to the source terminal of the first NMOS transistor, and a drain terminal;
a first resistor coupled between the drain terminal of the first NMOS transistor and a logic high node;
a second resistor coupled between the drain terminal of the second NMOS transistor and the logic high node; and
a third NMOS transistor having a gate terminal coupled to the drain terminal of the first NMOS transistor and not coupled to the second NMOS transistor, a source terminal coupled to a logic low node, and a drain terminal coupled to the source terminals of the first and second NMOS transistors. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification