Programming and erasing methods for a non-volatile memory cell

• US 6,928,001 B2
• Filed: 12/07/2000
• Issued: 08/09/2005
• Est. Priority Date: 12/07/2000
• Status: Expired due to Term

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Avni, Dror
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US09/730,586
• Publication Number:
  US 20040222437A1
• Time in Patent Office: 1,706 Days
• Field of Search: 365/185.22, 365/185.19, 365/185.28, 365/185.01
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

Claims

1. A method for programming a memory array, the method using programming pulses applied to either the drain or gate of one or more memory cells within said memory array, the method comprising:

adapting the duration or the amplitude of said programming pulses as a function of the difference between a present state of the one or more memory cells and a target state of the one or more memory cells, wherein the amplitude or duration of the programming pulses are correlated to the difference between a present state of the one or more memory cells and a target state of the one or more memory cells.

2. A method according to claim 1 wherein said step of adapting includes:

determining the voltage level of the programming pulse used to program a fast bit of said memory array having a relatively faster programming characteristic than other bits in said array; and

setting an initial programming pulse voltage level to a level near said programming pulse voltage level of said fast bit.

3. A method according to claim 2 and wherein said step of determining includes:

programming a small set of bits of said memory array;

setting a starting programming pulse voltage level to a programming pulse voltage level not higher than a programming pulse voltage level used to program a fast bit of said small set having a relatively faster programming characteristic than other bits in said small set;

programming generally all of the bits of said memory array using pulses having voltage levels beginning at said staring programming pulse voltage level; and

setting said initial programming pulse voltage level to a programming pulse level near a programming pulse voltage level used to program a bit having a relatively faster programming characteristic than generally all other bits of said array.

4. A method according to claim 2 wherein said initial programming pulse voltage level is not higher than said programming pulse level of said fast bit.

5. A method according to claim 3 wherein said generally all of bits of said array does not include bits of said small set.

6. A method according to claim 3 wherein said generally all of bits of said array does include bits of said small array.

7. A method according to claim 1 and wherein said step of adapting includes the steps of:

measuring the current threshold level of a bit to within a predetermined range; and

selecting an incremental voltage level of a next programming pulse for said bit in accordance with said measured current threshold level.

8. A method according to claim 7 and wherein said step of measuring includes the step of having multiple verify levels for said array.

9. A method according to claim 8 and wherein said step of measuring also includes the step of after a programming pulse, comparing a threshold level of a group of bits which have received said programming pulse to at least one of said verify levels and said step of selecting includes the step of selecting a next programming pulse level according to generally the highest verify level achieved by said group.

10. A method according to claim 9 and also comprising the steps of removing any bit which has been programmed from said group and repeating said steps of comparing and selecting until there are no more bits in said group.

11. A method according to claim 8 and wherein said step of measuring also includes the step of after a programming pulse, comparing a threshold level of a bit which received said programming pulse to at least one of said verify levels and said step of selecting includes the step of selecting a next programming pulse level according to generally the highest verify level achieved by said bit.

12. A method according to claim 7 and wherein the magnitude of said incremental voltage level corresponds to said measured current threshold level such that, after programming with said incremental voltage level, said bit generally is fully programmed.

13. A method according to claim 7 and wherein the magnitude of said incremental voltage level corresponds to said measured current threshold level such that, after programming with said incremental voltage level, said bit generally is slightly less than fully programmed.

14. A method according to claim 13 and also comprising the step of final programming said bit with a small incremental voltage level after said step of programming with said incremental voltage level.