Semiconductor device with non-volatile memory and random access memory

• US 6,928,512 B2
• Filed: 06/06/2002
• Issued: 08/09/2005
• Est. Priority Date: 06/20/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hoshi, Kouichi, Ayukawa, Kazushige, Miura, Seiji, Saitou, Yoshikazu, Iwamura, Tetsuya
• Primary Examiner(s): PORTKA, GARY J
• Application Number:
  US10/163,364
• Publication Number:
  US 20020199056A1
• Time in Patent Office: 1,160 Days
• Field of Search: 711/105, 711/106, 711/101, 365 51- 52, 365/63, 365/189.04, 365/222, 365/230.03
• US Class Current: 711/105
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06156 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.

Claims

1. A semiconductor device, comprising:

a first chip including a first memory comprised of a plurality of first memory cells each having a first capacitor and a first MISFET, a plurality of first nodes for receiving first access signals for said first memory, and a first control logic for controlling an operation of the first memory;

a second chip including a second memory comprised of a plurality of second memory cells each having a second capacitor and a second MISFET, a plurality of second nodes for receiving second access signals for said second memory, and a second control logic for controlling an operation of the second memory; and

a third chip including a memory controller comprised of a plurality of third nodes connected to said plurality of first nodes to supply the first access signals for said first chip, a plurality of fourth nodes connected to said plurality of second nodes to supply the second access signals for said second chip, and a plurality of fifth nodes for receiving external access signals,

wherein said memory controller delivers a first access signal so as to access said first memory when receiving the external access signal during a first period, and delivers a second access signal so as to access said second memory when receiving the external access signal during a second period,

wherein said memory controller outputs the first access signals indicating a refresh operation command to said plurality of first nodes of said first memory regardless of the external access signals.

wherein said memory controller outputs the second access signals indicating the refresh operation command to said plurality of second nodes of said second memory regardless of the external access signals,

wherein each of said first memory and said second memory is a dynamic random access memory chip, and

wherein said first chip, said second chip and said third chip are different chips.

2. A semiconductor device according to claim 1, wherein

during said first period, said memory controller responds to said external access signal to enable a read or write command signal for said first memory to be delivered as said first access signal and enable a refresh command signal for refreshing said second memory to be delivered as said second access signal;

and

during said second period, said memory controller responds to said external access signal to enable a read or write command signal for said second memory to be delivered as said second access signal and enable a refresh command signal for refreshing said first memory to be delivered as said first access signal.

3. A semiconductor device according to claim 2, wherein each of said first memory and second memory has a period for storing the same information in duplication.

4. A semiconductor device according to claim 1, wherein when write of data in said first memory occurs during said first period, said memory controller transcripts during said first period said write data to a second memory cell of corresponding address of said second memory in accordance with a predetermined procedure.

5. A semiconductor device according to claim 1, wherein said memory controller generates said first and second periods alternately on time sharing base.

6. A semiconductor device according to claim 1, wherein said semiconductor device alternately repeats said first period serving as a period for permission of read/write of said first memory and a period for refresh of said second memory and said second period serving as a period for refresh of said first memory and a period for permission of read/write of said second memory.

7. A semiconductor device according to claim 1, wherein

said third chip further includes an SRAM memory, and

said external access signals are supplied to said plurality of fifth nodes of said third chip with an SRAM interface method.

8. A semiconductor device according to claim 1 further comprising a molded device including therein said first, second and third chips, wherein

said molded device has a plurality of first electrodes electrically connecting to said third chip, and a plurality of second electrodes connected to said plurality of first electrodes to electrically connect to the outside of said molded device.

9. A semiconductor device according to claim 8, wherein

said molded device includes a substrate;

said first electrodes are provided on a first major surface of said substrate and said first, second and third chips are mounted on said first major surface;

said first major surface of said substrate is covered with a molding material; and

said second electrodes are provided on a second major surface of said substrate that is on the side opposite to said first major surface.

10. A semiconductor device according to claim 9, wherein said first, second and third chips are molded with resin.

11. A semiconductor device according to claim 1 further comprising a fourth chip including a non-volatile memory and a plurality of fifth nodes for receiving external access signals for said non-volatile memory, address signal terminals for receiving address signals from the outside of said semiconductor device, and a data input/output terminal for input/output of data to/from the outside of said semiconductor device, wherein

when said first and second memories of said first and second chips are accessed, a predetermined address and predetermined data are supplied via the address signal terminal and the data input/output terminal, and when the non-volatile memory block of said fourth chip is accessed, a predetermined address and predetermined data are supplied via the address signal terminal and the data input/output terminal.

12. A semiconductor device according to claim 11 further comprising a plurality of first control signal terminals supplied with signals for controlling access to said first and second memories, a plurality of second control signal terminals supplied with signals for controlling access to said non-volatile memory, and a plurality of power source terminals for said first to fourth semiconductor chips.

13. A semiconductor device according to claim 11, wherein each of said first and second chips performs read/write by a command synchronous with a clock, and said fourth chip is a flash memory chip.

14. A semiconductor devices comprising:

a first DRAM chip;

a second DRAM chip;

a chip including a memory controller comprised of a plurality of first nodes connected to said first DRAM chip to supply first access signals for said first DRAM chip, a plurality of second nodes adapted to supply second access signals for said second DRAM chip, and a plurality of third nodes for receiving external access signals;

a non-volatile memory chip;

a plurality of address signal terminals connected in common to said non-volatile memory chip and said chip including said memory controller to receive address signals from the outside of said semiconductor device; and

a plurality of data input/output terminals connected in common to said non-volatile memory chip and said chip including said memory controller to perform input/output of data from the outside of said semiconductor device,

wherein said memory controller outputs the first access signals and the second access signals indicating a refresh operation command regardless of the external access signals, and

wherein said first DRAM chip and said second DRAM chip are different chips.

15. A semiconductor device according to claim 14 further comprising a plurality of first control signal terminals to which signals for controlling access to said first and second DRAM chips are supplied as control signals to said memory controller, and a plurality of second control signal terminals to which signals for controlling access to said non-volatile memory are supplied.

16. A semiconductor device according to claim 15 further comprising a molded device including therein said first DRAM chip, said second DRAM chip and said chip including said memory controller, wherein

said plurality of address signal terminals, said plurality of data input/output terminals, said plurality of first control signal terminals and said plurality of second control signal terminals are exposed to the outside of said molded device.

17. A semiconductor device according to claim 16, wherein access from the outside of said semiconductor device to said first DRAM chip and second DRAM chip is carried out through an SRAM interface method and in the access from the outside of said semiconductor device, a busy period attributable to refresh of said first and second DRAM chips does not occur.

18. A semiconductor device according to claim 14, wherein said first and second memories have each a duplicate address space and store the same information in duplication.