Data input/output configuration for transfer among processing elements of different processors

• US 6,928,535 B2
• Filed: 07/16/2002
• Issued: 08/09/2005
• Est. Priority Date: 03/07/2000
• Status: Expired due to Term

• Current Assignee: Toshiba Electronic Devices & Storage Corporation (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamashita, Hirofumi, Sodini, Charles G.
• Primary Examiner(s): Kim, Kenneth S
• Application Number:
  US10/195,477
• Publication Number:
  US 20020195544A1
• Time in Patent Office: 1,120 Days
• Field of Search: 712/11, 712/20, 712/32, 712/225
• US Class Current: 712/225
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting element for converting incident light to an electric signal are arranged in a matrix, and a data read-out circuit having the same number of A/D converters as the number of the pixels arranged in one row of the array of pixel and serving to convert the analog signal converted by the pixels into a digital signal and to output the digital signal. The signal processing section includes plurality of processors. Each of the processors includes a plurality of processing elements (PE) provided on the A/D converter provided in the data read-out circuit by one to one. Moreover, a plurality of PEs provided in each of the processors have the same data processing function in the same processor. Furthermore, the PEs in the processor carry out a signal processing in parallel in response to an instruction.

Claims

1. A signal processing device comprising:

a plurality of processors, each of the processors including a plurality of processing elements having the same data processing function, each of the processors receiving a control signal, and the plurality of processing elements in the processor carrying out a data processing in parallel in response to the control signal;

a controller for giving the control signal to the processors; and

a plurality of data transfer lines provided for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other; and

wherein each of the plurality of processing elements comprises;

a memory circuit for storing data;

an arithmetic unit for receiving at least data read out from the memory circuit and performs an arithmetic operation; and

a data input/output unit, connected among the memory circuit, the arithmetic unit and one of the plurality of data transfer lines, for transmitting and receiving data among the memory circuit, the arithmetic unit and the one of the data transfer lines, the data input/output unit including a data input/output circuit, an output circuit having an input node connected to the data input/output circuit and an output node connected to the one data transfer line, and a switch circuit for taking in data, the switch circuit having one end connected to the data input/output circuit and the other end connected to the one data transfer line, wherein the output circuit within the processing element connected to the one data transfer line outputs data output from the associated data input/output circuit to the one data transfer line, and the switch circuit within at least one of the processing elements connected to the one data transfer line simultaneously inputs data on the one data transfer line to the associated data input/output circuit;

wherein the output circuit is a three-value output circuit, an output from which takes one of a logic 0 state, a logic 1 state and a high-impedance state,

each of the plurality of data transfer lines comprises a single wiring for transferring one-bit data, and

the output circuit within one of the processing elements connected to each of the plurality of data transfer lines outputs one of logic 0 data and logic 1 data to the data transfer line, the output circuits within the remaining ones of the processing elements connected to the same data transfer line takes the high-impedance state, and the switch circuit within at least one of the remaining ones of the processing elements connected to the same data transfer line simultaneously takes in data on the data transfer line.

2. The device according to claim 1, wherein the number of the processing elements in the processor is equal to that of the processors, and

the respective processing elements belonging to the processors which are different from each other are connected to the respective data transfer lines.

3. The device according to claim 1, wherein the processors receive the same control signal generated by the controller.

4. The device according to claim 1, wherein the processors receive control signals generated by the controller which are different from each other.

5. A signal processing device comprising:

a plurality of processors, each of the processors including a plurality of processing elements having the same data processing function, each of the processors receiving a control signal, and the plurality of processing elements in the processor carrying out a data processing in parallel in response to the control signal; and

a plurality of data transfer lines provided for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other,

wherein each of the plurality of processing elements includes;

a random access memory circuit divided into first and second memory circuit blocks;

a first signal input/output circuit provided to the first memory circuit block for reading data from the first memory circuit block and for writing data to the first memory circuit block;

a second signal input/output circuit provided to the second memory circuit block for reading data from the second memory circuit block and for writing data to the second memory circuit block;

an arithmetic unit for carrying out an operation on receipt of at least output data from the first and second signal input/output circuits;

a first data transfer path for giving a result of the operation to the first and/or second signal input/output circuits;

a second data transfer path for giving a result of the operation by the arithmetic unit to the other processing elements in the same processor and giving data from the other processing elements in the same processor to the arithmetic unit;

a data output circuit, connected to the first data transfer path and one of the plurality of data transfer lines, for receiving data from the first data transfer path and for transmitting the data to the one data transfer line; and

a switch circuit connected between one of the plurality of data transfer lines and the first data transfer path, for receiving data from the one data transfer line and for transmitting the data to the first data transfer path,

wherein one of a plurality of the data output circuits connected to one data transfer line outputs data on the associated first data transfer path to the data transfer line, and at least two of a plurality of the switch circuits connected to the one data transfer line input data on the data transfer line to the first data transfer path; and

wherein the first and second memory circuit blocks are operated by shifting the phases of the data reading and writing cycles by a half cycle.

6. A signal processing device comprising:

a plurality of processors, each of the processors including a plurality of processing elements having the same data processing function, each of the processors receiving a control signal, and the plurality of processing elements in the processor carrying out a data processing in parallel in response to the control signal; and

a plurality of data transfer lines provided for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other,

wherein each of the plurality of processing elements includes;

a memory circuit for storing data;

an arithmetic unit for receiving at least data read out from the memory circuit and performs an arithmetic operation; and

a data input/output unit, connected among the memory circuit, the arithmetic unit and one of the plurality of data transfer lines, for transmitting and receiving data among the memory circuit, the arithmetic unit and the one of the data transfer lines, the data input/output unit including a data input/output circuit, an output circuit having an input node connected to the data input/output circuit and an output node connected to the one data transfer line, and a switch circuit for taking in data, the switch circuit having one end connected to the data input/output circuit and the other end connected to the one data transfer line, wherein data output from the data input/output circuit associated with the output circuit within the processing element connected to the one data transfer line is output to the one data transfer line, and the switch circuit within at least one of the processing elements connected to the one data transfer line inputs data on the one data transfer line to the associated data input/output circuit; and

wherein the output circuit is a three-value output circuit, an output from which takes one of a logic 0 state, a logic 1 state and a high-impedance state,

each of the plurality of data transfer lines comprises a single wiring for transferring one-bit data, and

the output circuit within one of the processing elements connected to each of the plurality of data transfer lines outputs one of logic 0 data and logic 1 data to the data transfer line, the output circuits within the remaining ones of the processing elements connected to the same data transfer line takes the high-impedance state, and the switch circuit within at least one of the remaining ones of the processing elements connected to the same data transfer line simultaneously takes in data on the data transfer line.

7. A signal processing device comprising:

a plurality of processors, each of the processors including a plurality of processing elements having the same data processing function, each of the processors receiving a control signal, and the plurality of processing elements in the processor carrying out a data processing in parallel in response to the control signal;

a controller for giving the control signal to the processors; and

a plurality of data transfer lines provided for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other; and

wherein each of the plurality of processing elements includes;

a random access memory circuit divided into first and second memory circuit blocks;

a first signal input/output circuit provided to the first memory circuit block for reading data from the first memory circuit block and for writing data to the first memory circuit block;

a second signal input/output circuit provided to the second memory circuit block for reading data from the second memory circuit block and for writing data to the second memory circuit block;

an arithmetic unit for carrying out an operation on receipt of an output from the first and second signal input/output circuits and data transferred from the other processing elements through the plurality of data transfer lines;

a first data transfer path for giving data transferred from other processing elements to the arithmetic unit;

a second data transfer path for giving a result of the operation to the first and second signal input/output circuits; and

a third data transfer path for transferring the result of the operation in the arithmetic unit to the other processing elements,

wherein the first and second memory circuit blocks are operated by shifting phases of data reading and writing cycles.

8. The device according to claim 7, wherein the number of the processing elements in the processor is equal to that of the processors, and

the respective processing elements belonging to the processors which are different from each other are connected to the respective data transfer lines.

9. The device according to claim 7, wherein the processors receive the same control signal generated by the controller.

10. The device according to claim 7, wherein the processors receive control signals generated by the controller which are different from each other.

11. The device according to claim 7, wherein the first and second memory circuit blocks are operated by shifting the phases of the data reading and writing cycles by a half cycle.

12. The device according to claim 7, wherein data for one bit are read from the first and second memory circuit blocks, the arithmetic unit sequentially carries out an operation every bit, odd-numbered data bits of the results of the operation are stored in one of the first and second memory circuit block and even-numbered data bits of the results of the operation are stored in the other memory circuit block.

13. A signal processing device comprising:

a plurality of processors, each of the processors including a plurality of processing elements having the same data processing function, each of the processors receiving a control signal, and the plurality of processing elements in the processor carrying out a data processing in parallel in response to the control signal; and

a plurality of data transfer lines provided for mutually transferring data between the plurality of processing elements belonging to the processors which are different from each other,

wherein each of the plurality of processing elements includes;

a random access memory circuit divided into first and second memory circuit blocks;

a first signal input/output circuit provided to the first memory circuit block for reading data from the first memory circuit block and for writing data to the first memory circuit block;

a second signal input/output circuit provided to the second memory circuit block for reading data from the second memory circuit block and for writing data to the second memory circuit block;

an arithmetic unit for carrying out an operation on receipt of at least output data from the first and second signal input/output circuits;

a first data transfer path for giving a result of the operation to the first and/or second signal input/output circuits;

a second data transfer path for giving a result of the operation by the arithmetic unit to the other processing elements in the same processor and giving data from the other processing elements in the same processor to the arithmetic unit;

a data output circuit, connected to the first data transfer path and one of the plurality of data transfer lines, for receiving data from the first data transfer path and for transmitting the data to the one data transfer line; and

a switch circuit connected between one of the plurality of data transfer lines and the first data transfer path, for receiving data from the one data transfer line and for transmitting the data to the first data transfer path,

wherein one of a plurality of the data output circuits connected to one data transfer line outputs data on the associated first data transfer path to the data transfer line, and at least two of a plurality of the switch circuits connected to the one data transfer line input data on the data transfer line to the first data transfer path; and

wherein data for one bit are read from the first and second memory circuit blocks, the arithmetic unit sequentially carries out an operation every bit, odd-numbered data bits of the results of the operation are stored in one of the first and second memory circuit blocks and even-numbered data bits of the results of the operation are stored in the other memory circuit block.