IC layout having topological routes

• US 6,928,633 B1
• Filed: 08/14/2002
• Issued: 08/09/2005
• Est. Priority Date: 01/22/2002
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Caldwell, Andrew
• Primary Examiner(s): WHITMORE, STACY
• Application Number:
  US10/219,608
• Time in Patent Office: 1,091 Days
• Field of Search: 716 11- 14
• US Class Current: 716/130
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Some embodiments of the invention provide an integrated circuit (“IC”) design layout that includes topological routes. This layout includes several nets, each with a set of routable elements in the IC design-layout region. For each net, this layout also includes a topological route that connects the net'"'"'s routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes. In some embodiments, the IC layout further includes a topological graph that represents the IC design layout topologically. The topological graph includes several topological items including a set of items for each net that represent the net'"'"'s routable elements. Each net'"'"'s topological route specifies an associated set of items in the topological graph.

Claims

1. An integrated circuit (“

IC”

) design layout comprising;

a) a plurality of nets, each net has a set of routable elements in the IC design-layout region; and

b) for each net, a topological route that connects the net'"'"'s routable elements, wherein each topological route is a route that represents a set of diffeomorphic geometric routes.

2. The IC design layout of claim 1 further comprising:

a topological graph that represents the IC design layout topologically, wherein the topological graph includes a plurality of topological items including a set of items for each net that represent the net'"'"'s routable elements;

wherein each net'"'"'s topological route specifies an associated set of items in the topological graph.

3. The IC design layout of claim 2, wherein the associated set of items for at least one of the nets includes at least one item that represents a via.

4. The IC design layout of claim 2, wherein the topological graph is a tessellated graph that includes a plurality of nodes and a plurality of edges, wherein each edge is between a pair of nodes.

5. The IC design layout of claim 4, wherein the layout has a coordinate system with at least two coordinate axes, wherein the tessellated graph is a triangulated graph that includes a plurality of edges, wherein at least some of the edges are not aligned with either coordinate axis.

6. The IC design layout of claim 4, wherein the associated set of items for at least one net includes items along edges of the tessellated graph.

7. The IC design layout of claim 6, wherein the associated set of items for at least one net includes nodes in the tessellated graph.

8. The IC design layout of claim 7, wherein the tessellated graph includes a plurality of faces, wherein certain items in the topological graph are vias, wherein the associated sets of items for a net'"'"'s route includes a region inside a face that is suitable for containing a via.

9. The IC design layout of claim 8, wherein the region inside the face that is suitable for containing a via is the overlap of two regions within two faces on two different layers of the tessellated graph.

10. The IC design layout of claim 8, wherein the region for the via is identified before identifying the topological route for the net that uses the via.

11. The IC design layout of claim 8, wherein the region for the via is identified while defining the topological route that uses the via.

12. The IC design layout of claim 1, wherein the layout represents the design of a portion of a single IC.

13. The IC design layout of claim 1, wherein the layout represents the design of a single IC.

14. An integrated circuit (“

IC”

) design layout comprising a topological route that connects routable elements of a net, wherein the topological route represents a set of diffeomorphic geometric routes.

15. The IC design layout of claim 14 further comprising a plurality of topological routes, wherein each particular route connects routable elements of a particular net, wherein each topological route is a route that represents a set of diffeomorphic geometric routes.

16. The IC design layout of claim 14, wherein the topological route is specified as an associated set of items in the topological graph.

17. The IC design layout of claim 16 further comprising a topological graph that represents a decomposition of the IC design layout, wherein the topological graph includes a plurality of edges, wherein the associated set of items includes an associated set of intersections of the edges.

18. The IC design layout of claim 17, wherein the associated set of items further includes one item that represents a via.

19. The IC design layout of claim 18, wherein the topological graph further includes a plurality of faces, wherein the via is defined within a region in a face.

20. The IC design layout of claim 19, wherein the region inside the face that contains the via is at the intersection of two regions within two faces on two different layers of the topological graph.