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IC layout having topological routes

  • US 6,928,633 B1
  • Filed: 08/14/2002
  • Issued: 08/09/2005
  • Est. Priority Date: 01/22/2002
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit (“

  • IC”

    ) design layout comprising;

    a) a plurality of nets, each net has a set of routable elements in the IC design-layout region; and

    b) for each net, a topological route that connects the net'"'"'s routable elements, wherein each topological route is a route that represents a set of diffeomorphic geometric routes.

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