Method of making an ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge

• US 6,929,988 B2
• Filed: 10/01/2003
• Issued: 08/16/2005
• Est. Priority Date: 03/09/2001
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US10/678,444
• Publication Number:
  US 20040061171A1
• Time in Patent Office: 685 Days
• Field of Search: 438/192, 438/193, 438/195, 438/284, 257328-335
• US Class Current: 438/192
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Claims

1. A method for forming a semiconductor device with reduced Miller capacitance comprising the steps of:

heavily doping a substrate with a first conductivity dopant to form a drain region;

growing an epitaxial layer on the substrate and lightly doping the epitaxial layer with a dopant of the first conductivity;

implanting the surface of the epitaxial layer with dopants of a second polarity opposite in polarity to the first conductivity dopant;

covering the substrate with a trench mask having openings corresponding to desired trench regions and removing material from the exposed regions to form trenches;

growing an oxide layer of a substantially constant thickness on the trench walls and floor and diffusing the second conductivity dopant to form well regions adjacent the trench sidewalls;

forming over said oxide layer on said trench walls and floor upper and lower conductive layers respectively and separating the layers with a first dielectric layer;

removing a portion of said upper conductive layer; and

forming source regions on the surface of the epitaxial layer with dopant of the first conductivity.

2. The method of claim 1 comprising the further step of covering the wafer with a source metal region.

3. The method of claim 1 comprising the further step of connecting the source metal regions to the lower conductive trench layers at locations proximate the periphery of the semiconductor device.

4. The method of claim 1 wherein the dopant of the first conductivity is p-type and the dopant of the second conductivity is n-type.

5. The method of claim 1 wherein the dopant the first conductivity is n-type and the dopant of the second conductivity is p-type.

6. The method of claim 1 wherein the bottom of the upper conductive layer is approximately on the same level as the bottom of the well regions of second conductivity.

7. The method of claim 1 wherein the dielectric layer separating the two conductive layers is silicon nitride.

8. The method of claim 1 further comprising the step of adding a second interlevel dielectric layer above said upper conductive layer.

9. The method of claim 8 wherein said second interlevel dielectric layer is borophosphosilicate glass.