Semiconductor device and method of manufacturing the same

• US 6,930,382 B2
• Filed: 06/25/2004
• Issued: 08/16/2005
• Est. Priority Date: 12/27/2001
• Status: Expired due to Term

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sawada, Kanako, Sasaki, Keiichi
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Keshavan, Belur V.
• Application Number:
  US10/875,190
• Publication Number:
  US 20040235234A1
• Time in Patent Office: 417 Days
• Field of Search: 257/777, 257/621, 257/685, 257/686, 257/723, 257/737, 257/738, 257/758, 257/774, 257/778, 257/780, 438/109, 438/613, 438/624, 438/629, 438/637, 438/638, 438/639, 438/667, 438/672, 438/401, 438/973, 438/975, 438/107
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

A semiconductor device includes a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.

Claims

1. A semiconductor device comprising:

a first substrate including an element;

a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element;

a second substrate provided above the first substrate, and electrically connected with the element via the first plug; and

a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate, wherein the non-dielectric material and the conductive material comprise the same metal.

2. The semiconductor device according to claim 1, wherein the first and second substrates are a chip.

3. The semiconductor device according to claim 1, wherein the first substrate is a chip, and the second substrate is a substrate for mounting the chip.

4. The semiconductor device according to claim 1, wherein the second plug is provided at a corner of the first substrate.

5. The semiconductor device according to claim 1, wherein the second plug is a plug for detecting a thickness of the first substrate.

6. The semiconductor device according to claim 1, further comprising:

a bump provided between the first and second substrates, the first plug being connected to the element via the bump.

7. The semiconductor device according to claim 1, wherein the first and second substrates each include a multi-layer interconnection.

8. The semiconductor device according to claim 1, further comprising:

third and fourth plugs penetrating through the second substrate, the third plug being made of a conductive material, and the fourth plug being made of a non-dielectric material.

9. The semiconductor device according to claim 8, wherein the first and third plugs are electrically connected to each other, and the second and fourth plugs are not electrically connected to each other.

10. The semiconductor device according to claim 8, wherein the first to fourth plugs are made of the same material.

11. A semiconductor device comprising:

a first substrate including an element;

a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element;

a second substrate provided above the first substrate, and electrically connected with the element via the first plug; and

a second plug for detecting a thickness of the first substrate, the second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.

12. The semiconductor device according to claim 11, wherein the conductive material is metal, and the non-dielectric material is semiconductor.

13. The semiconductor device according to claim 11, wherein the first and second substrates are a chip.

14. The semiconductor device according to claim 11, wherein the first substrate is a chip, and the second substrate is a substrate for mounting the chip.

15. The semiconductor device according to claim 11, wherein the second plug is provided at a corner of the first substrate.

16. The semiconductor device according to claim 11, further comprising:

a bump provided between the first and second substrates, the first plug being connected to the element via the bump.

17. The semiconductor device according to claim 11, wherein the first and second substrates each include a multi-layer interconnection.

18. The semiconductor device according to claim 11, further comprising third and fourth plugs penetrating through the second substrate, the third plug being made of a conductive material, and the fourth plug being made of a non-dielectric material.

19. The semiconductor device according to claim 18, wherein the first and third plugs are electrically connected to each other, and the second and fourth plugs are not electrically connected to each other.

20. The semiconductor device according to claim 18, wherein the first to fourth plugs are made of the same material.