Digitizing ohmmeter system

• US 6,930,495 B1
• Filed: 06/16/2004
• Issued: 08/16/2005
• Est. Priority Date: 04/25/2003
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wan, Jun, Blom, Eric D., Urie, Stuart H., Holloway, Peter R.
• Primary Examiner(s): Nguyen, Vinh
• Assistant Examiner(s): Nguyen, Trung Q.
• Application Number:
  US10/870,200
• Time in Patent Office: 426 Days
• Field of Search: 324/712, 324/711, 324/710, 324/707, 324/691, 324/705, 324/158.1, 324/714, 324/723, 324/435, 324/74, 324/114, 324/134
• US Class Current: 324/712
• CPC Class Codes: G01R 27/02 Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant by measuring phase angle only G01R25/00

Abstract

A digitizing ohmmeter system for providing a digital resistance measurement includes a current source for providing an excitation current to an impedance-varying input sensor and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system utilizes synchronous AC excitation of the input sensor and an AC coupled analog-to-digital converter input. The digitizing ohmmeter system also implements correlated double sampling for noise cancellation to provide low noise and highly accurate analog-to-digital conversions. The ADC circuit includes a reference signal generator generating a resistance reference signal by time-sharing the excitation current with the input sensor. The digitizing ohmmeter system thereby realizes fully ratiometric operation such that neither a precise current source nor a precise voltage source is required for accurate resistance measurements.

Claims

1. A method for sampling and digitizing a resistance measurement from an impedance-varying input sensor, comprising:

applying a switched excitation source to said input sensor;

generating an input voltage step at said input sensor as a result of said application of said switched excitation source, said input voltage step being indicative of the resistance of said input sensor;

AC coupling said input voltage step to an integrator;

integrating charges corresponding to a transition of said input voltage step on an accumulation capacitor;

generating a fullscale resistance reference signal;

applying said fullscale resistance reference signal to said integrator;

generating a data dependent signal for deactivating or activating said integrator;

integrating a reference charge packet associated with a transition of said fullscale resistance reference signal when said data dependent signal has a first value or disregarding said reference charge packet when said data dependent signal has a second value, said transition of said fullscale resistance reference signal being opposite to said transition of said input voltage step;

comparing a signal corresponding to said charges accumulated on said accumulation capacitor with a reference level; and

generating an output signal as a result of said comparing, said data dependent signal having said first value and said second value corresponding to respective logical levels of said output signal,

wherein after a plurality of sampling cycles, said output signal forms a digital data stream having an ones density proportional to a ratio of the resistance of said input sensor to said fullscale resistance reference signal.

2. The method of claim 1, further comprising:

in response to a first clock signal, deactivating said integrator and operating said integrator in a correlated double sampling mode, said deactivating and operating comprising;

shorting out an amplifier in said integrator; and

storing an amplifier error voltage onto an input capacitor of said integrator, said amplifier error voltage comprising an amplifier offset voltage, 1/f noise and wideband amplifier noise.

3. The method of claim 1, wherein said comparing comprises:

coupling an inverting buffer to said accumulation capacitor;

generating at said inverting buffer a voltage corresponding to an inverted voltage value corresponding to said charges accumulated on said accumulation capacitor; and

comparing said voltage at said inverting buffer with said reference level.

4. The method of claim 1, wherein said AC coupling said input voltage step to an integrator comprises:

coupling said input voltage step to a first terminal of an input capacitor of said integrator;

coupling a second terminal of said input capacitor to an input terminal of an amplifier and a first terminal of said accumulation capacitor, said accumulation capacitor being coupled between said input terminal and an output terminal of said amplifier.

5. The method of claim 1, wherein said generating a fullscale resistance reference signal and said applying said fullscale resistance reference signal to said integrator comprise:

applying said switched excitation source to a reference resistor;

generating a voltage step at said reference resistor as a result of said application of said switched excitation source;

AC coupling said voltage step through a first capacitor to generate a reference charge packet.

6. The method of claim 1, wherein said generating a fullscale resistance reference signal and said applying said fullscale resistance reference signal to said integrator comprise:

applying said switched excitation source to said integrator for a first time interval, said first time interval being a small fraction of a time interval in which said switched excitation source is applied to said input sensor; and

generating a reference charge packet at said integrator as a result of said application of said switched excitation source to said integrator for said first time interval.

7. The method of claim 1, wherein said transition of said input voltage step comprises a rising edge of said input voltage step and said transition of said fullscale resistance reference signal comprises a falling edge of said fullscale resistance reference signal.

8. The method of claim 1, wherein said transition of said input voltage step comprises a falling edge of said input voltage step and said transition of said fullscale resistance reference signal comprises a rising edge of said fullscale resistance reference signal.

9. The method of claim 1, further comprising:

counting occurrences of ones in said digital data stream over a plurality of sampling cycles and generating a count value; and

subtracting an offset value from said count value to generate a resistance output value.

10. The method of claim 9, further comprising:

applying a first trim value to adjust a total number of sampling cycles for which said occurrences of ones are counted; and

applying a second trim value to adjust the value of said offset value.