Array of programmable cells with customized interconnections

• US 6,930,511 B2
• Filed: 08/11/2004
• Issued: 08/16/2005
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): Mai, Lam T.
• Application Number:
  US10/915,556
• Publication Number:
  US 20050012520A1
• Time in Patent Office: 370 Days
• Field of Search: 326 37- 41, 326/101
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Claims

1. A logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein;

at least some of said programmable cells are programmable by means of electrical signals supplied thereto; and

said customized interconnections comprise at least one metal layer comprising repeated subpatterns.

2. The logic array according to claim 1, wherein said programmable cells are customized by lithography.

3. A logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections providing interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein;

at least some of said programmable cells are programmable by means of electrical signals supplied thereto; and

said programmable cell includes a plurality of inverters, each selectably connected to at least one of said multiplicity of outputs.

4. The logic array according to claim 3, wherein said programmable cells are customized by lithography.

5. A logic array comprising:

an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and

customized interconnections providing interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs;

wherein;

at least some of said programmable cells are programmable by means of electrical signals supplied thereto;

at least some of said customized interconnections are customized by lithography; and

the functionality of at least some of said programmable cells as being either logic or memory is determined by a configuration of said customized interconnections.

6. The logic array according to claim 5, wherein said programmable cells are customized by lithography.

7. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis; and

at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer;

wherein

said at least first, second and third metal layers are part of a set of customized interconnections providing interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs; and

said third metal layer comprises at least one third metal layer strip extending generally perpendicular to said second metal layer strips and being connected thereto by a via.

8. The logic array according to claim 7, wherein said logic cells are programmable.

9. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis; and

at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer;

wherein

said at least first, second and third metal layers are part of a set of customized interconnections providing interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs; and

said third metal layer comprises at least one third metal layer strip extending generally parallel to said second metal layer strips and connecting two coaxial second metal layer strips by vias.

10. The logic array according to claim 9, wherein said logic cells are programmable.

11. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis; and

at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer;

wherein

said at least first, second and third metal layers are part of a set of customized interconnections providing interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs; and

each of at least some of said logic cells comprises at least one look-up table.

12. The logic array according to claim 11, wherein said logic cells are programmable.

13. A logic array comprising:

an array of programmable logic cells having a multiplicity of inputs and a multiplicity of outputs;

at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis; and

at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer;

wherein

said at least first, second and third metal layers are part of a set of customized interconnections providing permanent direct interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs; and

each of at least some of said logic cells includes at least one simple logic gate selectably connected to at least one of said multiplicity of outputs.

14. The logic array according to claim 13, wherein said programmable cells are customized by lithography.

15. A logic array comprising:

an array of logic cells having a multiplicity of inputs and a multiplicity of outputs;

at least first, second and third metal layers formed over said array of logic cells, said second metal layer comprising a plurality of generally parallel bands extending parallel to a first axis, each band comprising a multiplicity of second metal layer strips extending perpendicular to said first axis, and said first metal layer comprising a plurality of first metal layer strips extending perpendicular to a second axis; and

at least one via connecting at least one second metal layer strip with said first metal layer, said first metal layer underlying said second metal layer;

wherein

said at least first, second and third metal layers are part of a set of customized interconnections providing interconnections among at least a plurality of said multiplicity of inputs and at least a plurality of said multiplicity of outputs; and

each of at least some of said logic cells comprises at least one flip-flop.

16. The logic array according to claim 15, wherein said logic cells are programmable.

17. A semiconductor device comprising:

a logic array comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop, said logic array also comprising at least one standard metal layer, said standard metal layer comprises at least one metal strip, said metal strip having at least two vias overlying it; and

metal connection layers overlying said logic array for interconnecting various inputs and outputs thereof in a customized manner;

wherein

at least one interconnection within said logic cell is made by said metal connection layers; and

said logic cells also comprise at least one inverter, said inverter having an inverter input and an inverter output, wherein said inverter input and inverter output are part of said multiplicity of inputs and multiplicity of outputs.

18. The semiconductor device according to claim 17, wherein said logic cells are programmable.