Voltage booster
First Claim
Patent Images
1. A voltage booster for receiving a first voltage at an input and providing a boosted voltage at an output, the voltage booster comprising:
- a first capacitor having a first terminal for receiving a first clock signal and having a second terminal;
a second capacitor having a first terminal for receiving a second clock signal and having a second terminal, wherein the second clock signal is complementary to the first clock signal;
a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to receive the first voltage;
a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the first nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the first source/drain region of the first nFET, and the second source/drain region is coupled to the gate of the first nFET;
a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gate of the first nFET and the second source/drain region of the second nFET, the first source/drain region is coupled to the gates of the first and third nFETs and the second source/drain region of the second nFET, and the second source/drain region is coupled to the output of the voltage booster;
a fourth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to receive a control signal; and
a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the third nFET and the second source/drain region is coupled to receive the control signal.
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Abstract
Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.
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Citations
44 Claims
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1. A voltage booster for receiving a first voltage at an input and providing a boosted voltage at an output, the voltage booster comprising:
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a first capacitor having a first terminal for receiving a first clock signal and having a second terminal; a second capacitor having a first terminal for receiving a second clock signal and having a second terminal, wherein the second clock signal is complementary to the first clock signal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to receive the first voltage; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the first nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the first source/drain region of the first nFET, and the second source/drain region is coupled to the gate of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gate of the first nFET and the second source/drain region of the second nFET, the first source/drain region is coupled to the gates of the first and third nFETs and the second source/drain region of the second nFET, and the second source/drain region is coupled to the output of the voltage booster; a fourth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to receive a control signal; and a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the third nFET and the second source/drain region is coupled to receive the control signal. - View Dependent Claims (2, 3, 4)
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5. A pass circuit, comprising:
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a first input for receiving a clock signal; a second input for receiving a control signal; a third input for receiving an input voltage; an output for providing a boosted voltage; a logic circuit having a first input coupled to the first input of the pass circuit and a second input coupled to the second input of the pass circuit, wherein the logic circuit is adapted to provide complementary clock signals in response to the control signal having a first logic value and to be deactivated in response to the control signal having a second logic value; a first capacitor having a first terminal coupled to receive a first of the complementary clock signals and having a second terminal; a second capacitor having a first terminal coupled to receive a second of the complementary clock signals and having a second terminal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to receive the first voltage; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the first nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the first source/drain region of the first nFET, and the second source/drain region is coupled to the gate of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gate of the first nFET and the second source/drain region of the second nFET, the first source/drain region is coupled to the gates of the first and third nFETs and the second source/drain region of the second nFET, and the second source/drain region is coupled to the output of the pass circuit; a fourth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to the second input of the pass circuit; and a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the third nFET and the second source/drain region is coupled to the second input of the pass circuit. - View Dependent Claims (6, 7, 8)
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9. A voltage booster for receiving a first voltage at an input and providing a boosted voltage at an output, the voltage booster comprising:
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a first capacitor having a first terminal for receiving a first clock signal and having a second terminal; a second capacitor having a first terminal for receiving a second clock signal and having a second terminal, wherein the second clock signal is complementary to the first clock signal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to receive the first voltage; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the second source/drain region of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, and the first source/drain region is coupled to the first source/drain region of the first nFET; a fourth FET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the second source/drain region of the third nFET, and the second source/drain region is coupled to the gates of the first and second nFETs; and a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gates of the first and second nFETs and the second source/drain region of the fourth nFET, the first source/drain region is coupled to the gates of the first, second and fifth nFETs and the second source/drain region of the fourth nFET, and the second source/drain region is coupled to the output of the voltage booster. - View Dependent Claims (10, 11, 12, 13)
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14. A pass circuit, comprising:
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a first input for receiving a clock signal; a second input for receiving a control signal; a third input for receiving an input voltage; an output for providing a boosted voltage; a logic gate having a first input coupled to the first input of the pass circuit, a second input coupled to the second input of the pass circuit, and an output; a first inverter having an input coupled to the output of the logic gate and an output; a first capacitor having a first terminal coupled to the output of the logic gate and having a second terminal; a second capacitor having a first terminal coupled to the output of the first inverter and having a second terminal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the third input of the pass circuit; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the second source/drain region of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, and the first source/drain region is coupled to the first source/drain region of the first nFET; a fourth FET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the second source/drain region of the third nFET, and the second source/drain region is coupled to the gates of the first and second nFETs; a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gates of the first and second nFETs and the second source/drain region of the fourth nFET, the first source/drain region is coupled to the gates of the first, second and fifth nFETs and the second source/drain region of the fourth nFET, and the second source/drain region is coupled to the output of the pass circuit; a sixth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to receive a control signal; and a seventh nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the fifth nFET and the second source/drain region is coupled to receive the control signal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A memory device, comprising:
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an array of memory cells arranged in rows and columns, with pluralities of rows of memory cells grouped in blocks; a row decoder providing gate potentials to rows of the array of memory cells; pass gates coupled between the row decoder and the rows of the array of memory cells for selectively passing the gate potentials to their associated rows of the array of memory cells; a block decoder for selecting a target block of memory cells in response to a location address, wherein the block decoder comprises a pass circuit for controlling the pass gates of each block of the array of memory cells, each pass circuit comprising; a first capacitor having a first terminal for receiving a first clock signal and having a second terminal; a second capacitor having a first terminal for receiving a second clock signal and having a second terminal, wherein the second clock signal is complementary to the first clock signal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to receive a programming voltage; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the second source/drain region of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, and the first source/drain region is coupled to the first source/drain region of the first nFET; a fourth FET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the second source/drain region of the third nFET, and the second source/drain region is coupled to the gates of the first and second nFETs; and a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gates of the first and second nFETs and the second source/drain region of the fourth nFET, the first source/drain region is coupled to the gates of the first, second and fifth nFETs and the second source/drain region of the fourth nFET, and the second source/drain region is coupled to the associated pass gates. - View Dependent Claims (22)
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23. A memory device, comprising:
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an array of memory cells arranged in rows and columns, with pluralities of rows of memory cells grouped in blocks; a row decoder providing gate potentials to rows of the array of memory cells; pass gates coupled between the row decoder and the rows of the array of memory cells for selectively passing the gate potentials to their associated rows of the array of memory cells; a block decoder for selecting a target block of memory cells in response to a location address, wherein the block decoder comprises a pass circuit for controlling the pass gates of each block of the array of memory cells, each pass circuit comprising; a first input for receiving a clock signal; a second input for receiving a control signal indicative of whether the associated block is selected; a third input for receiving a programming voltage; an output coupled to the associated pass gates; a logic circuit having a first input coupled to the first input of the pass circuit and a second input coupled to the second input of the pass circuit, wherein the logic circuit is adapted to provide complementary clock signals when the associated block is selected; a first capacitor having a first terminal coupled to receive a first complementary clock signal and having a second terminal; a second capacitor having a first terminal coupled to receive a second complementary clock signal and having a second terminal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the third input of the pass circuit; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the second source/drain region of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, and the first source/drain region is coupled to the first source/drain region of the first nFET; a fourth FET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the second source/drain region of the third nFET, and the second source/drain region is coupled to the gates of the first and second nFETs; a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gates of the first and second nFETs and the second source/drain region of the fourth nFET, the first source/drain region is coupled to the gates of the first, second and fifth nFETs and the second source/drain region of the fourth nFET, and the second source/drain region is coupled to the output of the pass circuit; a sixth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to receive the control signal; and a seventh nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the fifth nFET and the second source/drain region is coupled to receive the control signal. - View Dependent Claims (24, 25, 26, 27)
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28. A method of programming a target memory cell of a memory device, comprising:
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selecting a block of memory cells containing the target memory cell, wherein each block includes a plurality of rows of memory cells and wherein each of the plurality of rows of memory cells is coupled to an n-channel field-effect transistor (nFET) pass gate; applying a programming voltage to a source/drain region of the nFET pass gate coupled to a row of memory cells containing the target memory cell; applying an intermediate voltage to a source/drain region of the nFET pass gates coupled to remaining rows of memory cells of the selected block; and applying a boosted voltage to gates of each of the nFET pass gates of the selected block, wherein the boosted voltage exceeds the programming voltage by at least one threshold voltage of the nFET pass gate and wherein the boosted voltage is generated by a single source.
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29. A method of programming a target memory cell of a memory device, comprising:
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selecting a block of memory cells containing the target memory cell, wherein each block includes a plurality of rows of memory cells, wherein each of the plurality of rows of memory cells is coupled to a first source/drain region of an n-channel field-effect transistor (nFET) pass gate and wherein the memory cells are floating-gate memory cells coupled in a NAND flash architecture; applying a programming voltage to a second source/drain region of the nFET pass gate coupled to a row of memory cells containing the target memory cell; applying an intermediate voltage to a second source/drain region of the nFET pass gates coupled to remaining rows of memory cells of the selected block; generating a boosted voltage using the programming voltage, wherein the boosted voltage exceeds the programming voltage by at least one threshold voltage of the nFET pass gates; and applying the boosted voltage to gates of each of the nFET pass gates of the selected block. - View Dependent Claims (30, 31)
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32. A method of programming a memory cell of a memory device, comprising:
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receiving a programming command and an address at the memory device, wherein the address is indicative of a target memory cell or memory cells of the memory device and wherein the memory cells are grouped in blocks each containing a plurality of word lines; decoding the address to identify target blocks and a target row within each target block containing the target memory cell or memory cells; activating a pass circuit for each target block, each pass circuit receiving a programming voltage; generating a boosted voltage on an output of each activated pass circuit, wherein the boosted voltage has a voltage level that exceeds the programming voltage; providing each boosted voltage to a plurality of pass gates, each pass gate coupled to a row of a target block; and providing the programming voltage to each target row through its associated pass gate receiving the boosted voltage.
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33. A pass circuit, comprising:
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a first input for receiving a clock signal; a second input for receiving a control signal; a third input for receiving an input voltage; an output for providing a boosted voltage; a NAND gate having a first input coupled to the first input of the pass circuit, a second input coupled to the second input of the pass circuit, and an output; a first inverter having an input coupled to the output of the NAND gate and an output; a first capacitor having a first terminal coupled to the output of the NAND gate and having a second terminal; a second capacitor having a first terminal coupled to the output of the first inverter and having a second terminal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to receive the first voltage; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the first nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the first source/drain region of the first nFET, and the second source/drain region is coupled to the gate of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gate of the first nFET and the second source/drain region of the second nFET, the first source/drain region is coupled to the gates of the first and third nFETs and the second source/drain region of the second nFET, and the second source/drain region is coupled to the output of the pass circuit; a fourth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to the second input of the pass circuit; and a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the third nFET and the second source/drain region is coupled to the second input of the pass circuit. - View Dependent Claims (34, 35, 36, 37)
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38. A memory device, comprising:
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an array of memory cells arranged in rows and columns, with pluralities of rows of memory cells grouped in blocks; a row decoder providing gate potentials to rows of the array of memory cells; pass gates coupled between the row decoder and the rows of the array of memory cells for selectively passing the gate potentials to their associated rows of the array of memory cells; a block decoder for selecting a target block of memory cells in response to a location address, wherein the block decoder comprises a pass circuit for controlling the pass gates of each block of the array of memory cells, each pass circuit comprising; a first input for receiving a clock signal; a second input for receiving a control signal indicative of whether the associated block is selected; a third input for receiving a programming voltage; an output coupled to the associated pass gates; a logic gate having a first input coupled to the first input of the pass circuit, a second input coupled to the second input of the pass circuit, and an output; a first inverter having an input coupled to the output of the logic gate and an output; a first capacitor having a first terminal coupled to the output of the logic gate and having a second terminal; a second capacitor having a first terminal coupled to the output of the first inverter and having a second terminal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the third input of the pass circuit; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to the second source/drain region of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, and the first source/drain region is coupled to the first source/drain region of the first nFET; a fourth FET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the second nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the second source/drain region of the third nFET, and the second source/drain region is coupled to the gates of the first and second nFETs; a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gates of the first and second nFETs and the second source/drain region of the fourth nFET, the first source/drain region is coupled to the gates of the first, second and fifth nFETs and the second source/drain region of the fourth nFET, and the second source/drain region is coupled to the output of the pass circuit; a sixth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to receive the control signal; and a seventh nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the fifth nFET and the second source/drain region is coupled to receive the control signal. - View Dependent Claims (39, 40, 41, 42, 43, 44)
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Specification