Hardware extensions for image and video processing

• US 6,930,689 B1
• Filed: 12/26/2000
• Issued: 08/16/2005
• Est. Priority Date: 12/26/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Daniel, Herve, Giacalone, Jean-Pierre
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/748,512
• Time in Patent Office: 1,694 Days
• Field of Search: 345/503, 345/520, 345/555, 375/240, 375/240.18, 375/240.2, 382/232, 382/233, 382/236, 382/235, 382/250, 398/14.13, 398/14.15, 398/394.1, 398/395.1, 398/402.1, 398/407.1, 398/415.1, 398/416.1
• US Class Current: 345/502
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: G06F 17/175 of multidimensional data
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A processing device (200) includes three hardware extensions: a motion estimation extension 202, a pixel interpolation extension 204 and a DCT/iDCT extension 206. The hardware extensions perform functions which would otherwise be highly processor intensive, resulting in high power consumption and/or low quality video/imaging processing. The processing device 200 could be used, for example, in a mobile videophone 150.

Claims

1. Circuitry for processing images and video, comprising:

a processor for executing software instructions for processing images or video;

a random access memory;

a motion estimation hardware accelerator coupled to said random access memory and the processor for performing motion estimation functions, responsive to a request by the processor, on data from the random access memory and returning a result to the processor for further processing of the video or images in the processor based on the result from the motion estimation hardware accelerator; and

a transform coding hardware accelerator coupled to said random access memory and the processor for performing transform coding functions, responsive to a request by the processor, on data from the random access memory and returning a result to the processor for further processing of the video or images in the processor based on the result from the transform coding hardware accelerator.

2. The circuitry of claim 1 and further comprising a pixel interpolation hardware accelerator coupled to said random access memory.

3. The circuitry of claim 2 wherein said pixel interpolation hardware accelerator performs a half-pixel interpolation function.

4. The circuitry of claim 1 wherein said motion estimation hardware accelerator includes circuitry for calculating a mean absolute difference function.

5. The circuitry of claim 1 wherein said transform coding hardware accelerator includes circuitry for calculating a direct cosine transform function.

6. The circuitry of claim 5 wherein said transform coding hardware accelerator includes circuitry for calculating an inverse direct cosine transform function.

7. A method of processing video information, comprising the steps of:

executing a compression task in a programmable processing device coupled to a random access memory;

upon encountering a motion estimation instruction, initiating execution of an associated function in a motion estimation hardware accelerator, said motion estimation hardware accelerator coupled to said processing device and said random access memory, such that the motion estimation hardware accelerator retrieves image data from the random access memory, performs a motion estimation function on the data, and returns a result to the processor for further processing of the compression task in the processor based on the result from the motion estimation hardware accelerator; and

upon encountering a transform coding instruction, initiating execution of an associated function in a transform coding hardware accelerator, said transform coding hardware accelerator coupled to said processing device and said random access memory, such that the transform coding hardware accelerator retrieves image data from the random access memory, performs a transform coding function on the data, and returns a result to the processor for further processing of the compression task in the processor based on the result from the transform coding hardware accelerator.

8. The method of claim 7 step of initiating execution of an associated function in the motion estimation hardware accelerator includes the step of retrieving image data from a data portion of said random access memory into said motion estimation hardware accelerator.

9. The method of claim 7 step of initiating execution of an associated function in the transform coding hardware accelerator includes the step of retrieving image data from a data portion of said random access memory into said transform coding hardware accelerator.

10. The method of claim 7 and further comprising the step of, upon encountering a pixel interpolation instruction, initiating execution of an associated function in a pixel interpolation hardware accelerator, said pixel interpolation hardware accelerator coupled to said processing device and said random access memory, such that the pixel interpolation hardware accelerator retrieves data from the random access memory, performs an interpolation function on the data, and returns a result to the processor.

11. The method of claim 10 wherein said step of initiating execution of an associated function in a pixel interpolation hardware accelerator includes the step of performing a half-pixel interpolation function.

12. The method of claim 7 wherein said step of initiating execution of an associated function in a motion estimation hardware accelerator includes the step of performing a mean absolute difference function.

13. The method of claim 7 wherein said step of initiating execution of an associated function in a transform coding hardware accelerator includes the step of performing a direct cosine transform function.

14. The method of claim 13 wherein said step of initiating execution of an associated function in a transform coding hardware accelerator includes the step of performing an inverse direct cosine transform function.

15. Circuitry for processing images and video, comprising:

a processor for executing a program of software instructions for processing images or video;

a random access memory coupled to said processor;

two or more hardware accelerators coupled to said processor, said hardware accelerators for performing certain video processing functions associated with ones of the software instructions; and

wherein certain software instructions can be processed by either the processor or by one of said hardware accelerators subsequent to said one of said hardware accelerators being enabled to process the certain software instructions where the decision to process the certain software instruction in the processor is made in real-time.