Arrangement of integrated circuits in a memory module

• US 6,930,903 B2
• Filed: 01/27/2004
• Issued: 08/16/2005
• Est. Priority Date: 03/07/2002
• Status: Expired due to Term

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Bhakta, Jayesh R., Pauley, Robert S. Jr.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/765,488
• Publication Number:
  US 20040184300A1
• Time in Patent Office: 567 Days
• Field of Search: 365/51, 365/63, 365/78, 711/2, 711/5, 711/104, 711/111, 711/115
• US Class Current: 365/63
• CPC Class Codes: H05K 1/0266 Marks, test patterns or identification means
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09409 Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
• CPC Class Codes: H05K 2201/09709 Staggered pads, lands or terminals; Parallel conductors in different planes
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

Claims

1. A memory module comprising:

a printed circuit board having a first lateral portion and a second lateral portion;

a plurality of identical integrated circuits mounted in a first row and a second row onto at least one surface of the printed circuit board;

a control logic bus connected to the plurality of identical integrated circuits, the control logic bus comprising a first set of address signal paths and a second set of address signal paths; and

a first register and a second register connected to the control logic bus, the first register accessing a first range and a second range of data bits, the second register accessing a third range and a fourth range of data bits, the first range and the second range of data bits being first and second non-contiguous subsets of a data word, and the third range and the fourth range of data bits being third and fourth non-contiguous subsets of the data word, wherein the first set of address signal paths connect the first register to the integrated circuits of the first row and the second row on the first lateral portion and the second set of address signal paths connect the second register to the integrated circuits of the first row and the second row on the second lateral portion.

2. The memory module of claim 1, wherein:

the first range of data bits comprise data bits 0 to 15;

the second range of data bits comprise data bits 32 to 47;

the third range of data bits comprise data bits 16 to 31; and

the fourth range of data bits comprise data bits 48 to 63.

3. The memory module of claim 1, wherein the printed circuit board has a line of bilateral symmetry which bisects the printed circuit board into a first lateral half and a second lateral half.

4. The memory module of claim 3, wherein the first row is substantially perpendicular to the line of bilateral symmetry.

5. The memory module of claim 4, wherein the first row is bilaterally symmetric with respect to the line of bilateral symmetry.

6. The memory module of claim 3, wherein the second row is substantially perpendicular to the line of bilateral symmetry.

7. The memory module of claim 6, wherein the second row is bilaterally symmetric with respect to the line of bilateral symmetry.

8. The memory module of claim 3, wherein the first set of address signal paths connect the integrated circuits of the first row and the second row on the first lateral half to the first register and the second set of address signal paths connect the integrated circuits of the first row and the second row on the second lateral half to the second register, the first set of address signal paths and the second set of address signal paths being bilaterally symmetric to one another across the line of bilateral symmetry.

9. The memory module of claim 1, wherein the first register addresses the identical integrated circuits located in the first row and in the second row on the first lateral portion of the printed circuit board, and the second register addresses the identical integrated circuits located in the first row and in the second row on the second lateral portion of the printed circuit board.

10. The memory module of claim 9, wherein the first lateral portion comprises a first lateral half of the printed circuit board and the second lateral portion comprises a second lateral half of the printed circuit board.

11. A method of accessing data bits of a data word, the method comprising:

providing a memory module comprising;

a printed circuit board having a first lateral portion and a second lateral portion;

a plurality of identical integrated circuits mounted in a first row and a second row onto at least one surface of the printed circuit board;

a control logic bus connected to the plurality of identical integrated circuits, the control logic bus comprising a first set of address signal paths connected to the integrated circuits of the first row and the second row on the first lateral portion and a second set of address signal paths connected to the integrated circuits of the first row and the second row on the second lateral portion; and

a first register and a second register connected to the control logic bus, wherein the first register is connected to the integrated circuits of the first row and the second row on the first lateral portion by the first set of address signal paths and the second register is connected to the integrated circuits of the first row and the second row on the second lateral portion by the second set of address signal paths;

accessing a first range of data bits and a second range of data bits using the first register, the first range and the second range of data bits being first and second non-contiguous subsets of the data word; and

accessing a third range of data bits and a fourth range of data bits using the second register, the third range and the fourth range of data bits being third and fourth non-contiguous subsets of the data word.

12. The method of claim 11, wherein:

the first range of data bits comprise data bits 0 to 15;

the second range of data bits comprise data bits 32 to 47;

the third range of data bits comprise data bits 16 to 31; and

the fourth range of data bits comprise data bits 48 to 63.

13. The method of claim 11, wherein the printed circuit board has a line of bilateral symmetry which bisects the printed circuit board into a first lateral half and a second lateral half.

14. The method of claim 13, wherein the first row is substantially perpendicular to the line of bilateral symmetry.

15. The method of claim 14, wherein the first row is bilaterally symmetric with respect to the line of bilateral symmetry.

16. The method of claim 13, wherein the second row is substantially perpendicular to the line of bilateral symmetry.

17. The method of claim 16, wherein the second row is bilaterally symmetric with respect to the line of bilateral symmetry.

18. The method of claim 13, wherein the first set of address signal paths connect the integrated circuits of the first row and the second row on the first lateral half to the first register and the second set of address signal paths connect the integrated circuits of the first row and the second row on the second lateral half to the second register, the first set of address signal paths and the second set of address signal paths being bilaterally symmetric to one another across the line of bilateral symmetry.

19. The method of claim 11, wherein the first register addresses the identical integrated circuits located in the first row and in the second row on the first lateral portion of the printed circuit board, and the second register addresses the identical integrated circuits located in the first row and in the second row on the second lateral portion of the printed circuit board.

20. The method of claim 19, wherein the first lateral portion comprises a first lateral half of the printed circuit board and the second lateral portion comprises a second lateral half of the printed circuit board.