Apparatus and method for synchronizing video and audio MPEG streams in a video playback device

• US 6,931,071 B2
• Filed: 08/31/2001
• Issued: 08/16/2005
• Est. Priority Date: 08/31/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Dhillon, Amandeep K., Haddad, Semir S.
• Primary Examiner(s): PHILIPPE, GIMS S
• Application Number:
  US09/943,793
• Publication Number:
  US 20030043924A1
• Time in Patent Office: 1,446 Days
• Field of Search: 375/240.28, 375/240.01, 375/240, 375/240.1, 370/498, 370/486, 370/473, 348/423.1, 704/500, 380/46
• US Class Current: 375/240.28
• CPC Class Codes: H04N 21/4135 external recorder interface circuits between an apparatus for recording television signals and a television receiver H04N5/775
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/4348 Demultiplexing of additional data and video streams
• CPC Class Codes: H04N 5/76 Television signal recording
• CPC Class Codes: H04N 5/781 on disks or drums
• CPC Class Codes: H04N 5/85 on discs or drums
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

There is disclosed an MPEG decoder comprising: 1) a packetized elementary stream (PES) interface for receiving a plurality of packetized elementary streams associated with a single video program; 2) a presentation time stamp (PTS) detection circuit for detecting presentation time stamps in the packetized elementary streams and extracting the presentation time stamps therefrom; and 3) a selection circuit for selecting presentation time stamps associated with a first one of the plurality of packetized elementary streams and transmitting the selected presentation time stamps to a clock generation circuit, wherein the clock generation circuit generates a first reference clock signal used by a first decoder to decode the first packetized elementary stream. The clock generation circuit further generates a second reference clock signal synchronized to the first reference clock signal, wherein the second reference clock signal is used by a second decoder to decode a second packetized elementary stream in synchronization with the first packetized elementary stream.

Claims

1. An MPEG decoder comprising:

a packetized elementary stream (PES) interface capable of receiving a plurality of packetized elementary streams associated with a single video program;

a presentation time stamp (PTS) detection circuit capable of detecting presentation time stamps in said packetized elementary streams and extracting said presentation time stamps therefrom; and

a selection circuit capable of selecting presentation time stamps associated with a first one of said plurality of packetized elementary streams and transmitting said selected presentation time stamps to a clock generation circuit, wherein said clock generation circuit generates a first reference clock signal used by a first decoder to decode said first packetized elementary stream.

2. The MPEG decoder as set forth in claim 1 wherein said clock generation circuit further generates a second reference clock signal synchronized to said first reference clock signal and wherein said second reference clock signal is used by a second decoder to decode a second packetized elementary stream in synchronization with said first packetized elementary stream.

3. The MPEG decoder as set forth in claim 2 wherein said selected presentation time stamps are video presentation times stamps and said first decoder is a video decoder.

4. The MPEG decoder as set forth in claim 3 wherein said second decoder is an audio decoder.

5. The MPEG decoder as set forth in claim 2 wherein said selected presentation time stamps are audio presentation times stamps and said first decoder is an audio decoder.

6. The MPEG decoder as set forth in claim 5 wherein said second decoder is a video decoder.

7. The MPEG decoder as set forth in claim 2 said clock generation circuit generates said second reference clock signal by synchronizing presentation time stamps associated with said second packetized elementary stream with said selected presentation time stamps associated with said first packetized elementary stream.

8. A digital video recorder capable of playing back a recorded television program stored as packetized elementary streams, said digital video recorder comprising:

a video processor capable of receiving an incoming television program and converting said incoming television program to a baseband video signal capable of being displayed on a television set coupled to said digital video recorder;

a storage disk capable of storing said incoming television program as packetized elementary streams during recording; and

an MPEG decoder comprising;

a packetized elementary stream (PES) interface capable of receiving a plurality of packetized elementary streams associated with said recorded television program from said storage disk during playback;

a presentation time stamp (PTS) detection circuit capable of detecting presentation time stamps in said packetized elementary streams and extracting said presentation time stamps therefrom; and

a selection circuit capable of selecting presentation time stamps associated with a first one of said plurality of packetized elementary streams and transmitting said selected presentation time stamps to a clock generation circuit, wherein said clock generation circuit generates a first reference clock signal used by a first decoder to decode said first packetized elementary stream.

9. The digital video recorder as set forth in claim 8 wherein said clock generation circuit further generates a second reference clock signal synchronized to said first reference clock signal and wherein said second reference clock signal is used by a second decoder to decode a second packetized elementary stream in synchronization with said first packetized elementary stream.

10. The digital video recorder as set forth in claim 9 wherein said selected presentation time stamps are video presentation times stamps and said first decoder is a video decoder.

11. The digital video recorder as set forth in claim 10 wherein said second decoder is an audio decoder.

12. The digital video recorder as set forth in claim 9 wherein said selected presentation time stamps are audio presentation times stamps and said first decoder is an audio decoder.

13. The digital video recorder as set forth in claim 12 wherein said second decoder is a video decoder.

14. The digital video recorder as set forth in claim 9 said clock generation circuit generates said second reference clock signal by synchronizing presentation time stamps associated with said second packetized elementary stream with said selected presentation time stamps associated with said first packetized elementary stream.

15. For use in a digital video recorder, a method for decoding a television program stored in MPEG format:

receiving in an MPEG decoder a plurality of packetized elementary streams associated with the stored television program;

detecting presentation time stamps in the packetized elementary streams;

extracting the presentation time stamps from the packetized elementary streams;

selecting presentation time stamps associated with a first one of the plurality of packetized elementary streams; and

generating from the selected presentation time stamps a first reference clock signal used by a first decoder to decode the first packetized elementary stream.

16. The method as set forth in claim 15 further comprising the step of generating a second reference clock signal synchronized to the first reference clock signal, wherein the second reference clock signal is used by a second decoder to decode a second packetized elementary stream in synchronization with the first packetized elementary stream.

17. The method as set forth in claim 15 wherein the selected presentation time stamps are video presentation times stamps and the first decoder is a video decoder.

18. The method as set forth in claim 16 wherein the second decoder is an audio decoder.

19. The method as set forth in claim 15 wherein the selected presentation time stamps are audio presentation times stamps and the first decoder is an audio decoder.

20. The method as set forth in claim 16 wherein the second decoder is a video decoder.

21. The method as set forth in claim 16 wherein the step of generating a second reference clock signal comprises the sub-step of synchronizing presentation time stamps associated with the second packetized elementary stream with the selected presentation time stamps associated with the first packetized elementary stream.