Phase-locked loop with analog phase rotator

• US 6,931,089 B2
• Filed: 08/21/2001
• Issued: 08/16/2005
• Est. Priority Date: 08/21/2001
• Status: Expired due to Fees

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Zheng, Dong, Wu, Bin
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): File, Erin M.
• Application Number:
  US09/934,632
• Publication Number:
  US 20030039329A1
• Time in Patent Office: 1,456 Days
• Field of Search: 375/376, 327/248, 327/361
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal and provides first and second periodic signals each having a frequency that is a function of the phase difference, the first and second periodic signals being 90 degrees out of phase with each other. An interpolator circuit then linearly combines the first and second periodic signals with third and fourth periodic signals to provide the first internal periodic signal. The interpolator circuit may provide a second internal periodic signal that is 90 degrees out of phase relative to the first internal periodic signal. The phase-locked loop may further include a low-pass filter provided between the phase detector and the rotator.

Claims

1. A phase-locked loop, comprising:

a phase detector receiving an input signal and a first internal periodic signal and providing a phase signal indicative of a phase difference between said input signal and said first internal periodic signal;

a rotator receiving said phase signal and providing a first periodic signal and a second periodic signal each having a period being a function of said phase difference, said first and said second periodic signals being 90 degrees out of phase relative to each other said rotator further comprising an enforcer which adjusts the amplitudes of the first periodic signal and the second periodic signal to within predetermined limits; and

an interpolator circuit linearly combining said first and second periodic signals with a third periodic signal and a fourth periodic signal to provide said first internal periodic signal.

2. A phase-locked loop as in claim 1, wherein said interpolator circuit further providing a second internal periodic signal, said second internal periodic signal being 90 degrees out of phase relative to said first internal periodic signal.

3. A phase-locked loop as in claim 1, further comprising a low-pass filter provided between said phase detector and said rotator.

4. A phase-locked loop as in claim 2 wherein said rotator comprises an integrator.

5. A phase-locked loop as in claim 1, wherein said first (Q) and second (I) periodic signals are given by the equations:

Q=A cos(kf(p))

I=A sin(kf(p))

where A is an amplitude of each of signals Q and I, k is a gain of said rotator circuit, and f(p) represents a function of said phase difference.

6. A phase-locked loop as in claim 5, wherein said phase difference is represented in said phase signal as a voltage.

7. A phase-locked loop as in claim 5, wherein said function comprises integration.

8. A phase-locked loop as in claim 1, wherein said third and fourth periodic signals each have a frequency being substantially a frequency of said input signal.

9. A phase-locked loop as in claim 5, wherein said enforcer provides an error signal indicating a deviation in said first and second periodic signals from said equations.

10. A phase-locked loop as in claim 9, wherein said error signal is a function of the value Δ

=r²−

I²−

Q², where r is an amplitude of each of signals land Q.

11. A phase-locked loop as in claim 5 wherein said third (x) and fourth (y) periodic signals are given by the equations:

 

x=sin ω

t,

y=cos ω

t,

where ω

represents a frequency of said third and fourth periodic signals.

12. A phase-locked loop as in claim 11, wherein said first internal periodic signal S(t) is given by:

S(t)=sin(ω

t−

φ

),

where φ

is indicative of said phase difference.

13. A method for providing a phase-locked loop, comprising:

receiving an input signal and a first internal periodic signal and providing a phase signal indicative of a phase difference between said input signal and said first internal periodic signal;

receiving said phase signal and providing a first periodic signal and a second periodic signal each having a period being a function of said phase difference, said first and said second periodic signals being 90 degrees out of phase relative to each other;

adjusting the amplitudes of the first periodic signal and the second periodic signal to within predetermined limits; and

linearly combining said first and second periodic signals with a third periodic signal and a fourth periodic signal to provide said first internal periodic signal.

14. A method for providing a phase-locked loop as in claim 13, further providing a second internal periodic signal, said second internal periodic signal being 90 degrees out of phase relative to said first internal periodic signal.

15. A method for providing a phase-locked loop as in claim 13, further comprising providing a low-pass filter between said phase detector and said rotator.

16. A method for providing a phase-locked loop as in claim 14 wherein said rotator comprises an integrator.

17. A method for providing a phase-locked loop as in claim 13, wherein said first (Q) and second (I) periodic signals are given by the equations:

Q=A cos(kf(p))

I=A sin(kf(p))

where A is an amplitude of each of signals Q and I, k is a gain of said rotator circuit, and f(p) represents a function of said phase difference.

18. A method for providing a phase-locked loop as in claim 17, wherein said phase difference is represented in said phase signal as a voltage.

19. A method for providing a phase-locked loop as in claim 17, wherein said function comprises integration.

20. A method for providing a phase-locked loop as in claim 13, wherein said third and fourth periodic signals each have a frequency being substantially a frequency of said input signal.

21. A method for providing a phase-locked loop as in claim 17, wherein said adjusting comprises providing an error signal indicating a deviation in said first and second periodic signals from said equations.

22. A method for providing a phase-locked loop as in claim 17, wherein said error signal is a function of the value Δ

=r²−

I²−

Q², where r is an amplitude of each of signals I and Q.

23. A method for providing a phase-locked loop as in claim 17, wherein said third (x) and fourth (y) periodic signals are given by the equations:

x=sin ω

t,

y=cos ω

t,

where ω

represents a frequency of said third and fourth periodic signals.

24. A method for providing a phase-locked loop as in claim 23, wherein said first internal periodic signal S(t) is given by:

S(t)=sin(ω

t−

φ

),

where φ

is indicative of said phase difference.