Status register architecture for flexible read-while-write device

• US 6,931,498 B2
• Filed: 04/03/2001
• Issued: 08/16/2005
• Est. Priority Date: 04/03/2001
• Status: Expired due to Term

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Panavich, Jason, Ganesan, Ramkarthik, Kendall, Terry L., Talreja, Sanjay S.
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Song, Jasmine
• Application Number:
  US09/827,134
• Publication Number:
  US 20020144066A1
• Time in Patent Office: 1,596 Days
• Field of Search: 711/103, 711/154, 711/156, 711/173, 711/171, 711/172, 711/5, 711/168, 711/169
• US Class Current: 711/154
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.

Claims

1. An integrated circuit comprising:

a memory array having at least a first plane and a second plane, wherein a first partition of the memory array comprises one of the planes and a second partition of the memory array comprises the remaining planes, wherein a write operation is to be performed on the first partition and a read operation is to be concurrently performed on the second partition; and

a status register coupled to the memory array, wherein the status register is to provide status information for at least the first and second partition, the statue register being responsive to a memory address associated with one of the first and second partitions to indicate a status of the addressed partition.

2. The integrated circuit of claim 1, further comprising:

a microcontroller coupled to the status register, wherein the microcontroller supplies control signals to the status register.

3. The integrated circuit of claim 2, further comprising:

an user interface coupled to the status register, wherein the user interface is to communicate status register information to be used to decide subsequent operations.

4. The integrated circuit of claim 1, wherein the at least first and second planes comprise substantially equal memory storage capacities.

5. A method of reading while writing to a memory array, comprising:

dividing the memory array into n planes, wherein n is an integer greater than one;

defining a write partition, wherein the write partition is a single plane of the memory array;

defining a read partition, wherein the read partition is made up of all of the remaining n-1 plane, of the memory array; and

providing the status of the read partition and the write partition of the memory array with a single status register, wherein providing the status includes providing the status of the read partition responsive to receiving an address associated with the read partition and providing the status of the write partition responsive to receiving an address associated with the write partition.

6. The method of claim 5, wherein the memory array consists of multiple memory planes having substantially equal storage capacity.

7. The method of claim 6, wherein the multiple memory planes consist of nonvolatile memory cells.

8. The method of claim 7, wherein the nonvolatile memory cell is a flash memory cell.

9. The method of claim 6, wherein the writs partition has a dynamic memory address, wherein the memory address changes any time a program or erase operation begins or resumes in a new memory piano.

10. The method of claim 6, wherein if no program or erase operation is performed, the read partition and the write partition are allocated to the same memory location.

11. An apparatus comprising:

means for partitioning a memory array into a fixed first partition and a variable second partition to enable multiple operations to be performed on the memory array at the same time; and

means for monitoring the operations performed on the memory array, the means for monitoring including a register to provide status information for at least the first and second partition, the status register being responsive to a memory address associated with one of the first and second partitions to indicate a status of the addressed partition.

12. The apparatus of claim 11 further comprising a means for communicating the status of the operations performed on the memory array to a user.