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Status register architecture for flexible read-while-write device

  • US 6,931,498 B2
  • Filed: 04/03/2001
  • Issued: 08/16/2005
  • Est. Priority Date: 04/03/2001
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • a memory array having at least a first plane and a second plane, wherein a first partition of the memory array comprises one of the planes and a second partition of the memory array comprises the remaining planes, wherein a write operation is to be performed on the first partition and a read operation is to be concurrently performed on the second partition; and

    a status register coupled to the memory array, wherein the status register is to provide status information for at least the first and second partition, the statue register being responsive to a memory address associated with one of the first and second partitions to indicate a status of the addressed partition.

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