Rapid fail analysis of embedded objects

• US 6,931,580 B1
• Filed: 03/13/2000
• Issued: 08/16/2005
• Est. Priority Date: 03/13/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Quandt, Kevin C., Barcomb, Kevin J., Olive, Mark F., Huisman, Leendert M.
• Primary Examiner(s): Chung, Phung My
• Application Number:
  US09/524,254
• Time in Patent Office: 1,982 Days
• Field of Search: 714/742, 714/723, 714/25, 714/725, 714/733, 714/727, 714/734, 382/149
• US Class Current: 714/742
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A method for analyzing test data for objects on an IC or a wafer is provided. The test data is linked to available layout information about the object under test. Certain objects are selected based on the test data. A representation of the selected objects is placed on a map of the IC or on a map of the wafer. The representation should correspond to the physical location of the object on the IC or wafer. Preferably, the representation comprises one or more polygons that enclose all devices that make up the object.

Claims

1. A method of mapping test results for objects on a semiconductor wafer comprising:

a) performing a first level test;

b) selecting failed objects based on the test results;

c) placing representations of the selected failed objects on a visual map according to the selected objects'"'"' positions on the wafer.

2. The method of claim 1 wherein step b) comprises:

determining locations of each the objects;

creating representations enclosing the objects;

building a cross-reference map linking the test results to the locations of the representations; and

referring to the cross-reference map when placing the representations on the map.

3. The method of claim 1 wherein the representations are polygons enclosing all devices which make up the selected object.

4. The method of claim 1 wherein the map is a wafer map.

5. The method of claim 1 wherein the map is a map of an IC.

6. The method of claim 1 wherein the map is a set of coordinates.

7. The method of claim 1, wherein step b) comprises:

physically plotting the location and shape of the failed objects on the visual map of the wafer.

8. A method for determining the physical locations of failed objects on an integrate circuit comprising:

a) identifying objects on the integrated circuit, which are to be tested;

b) determining a location of each of the objects;

c) providing test data resulting from a test of the integrated circuit;

d) selected failed objects based on the test data; and

e) linking the location of the selected failed objects with the test data to determine a physical location of the selected failed objects on the integrated circuit.

9. The method of claim 8 wherein step b) comprises:

constructing a set of polygons to enclose each object separately; and

building a cross-reference map linking the polygons and the locations of the objects; and

wherein step c) comprises;

looking up locations of the polygons in the cross-reference map; and

building a wafer map of the selected objects.

10. The method of claim 9 further comprising analyzing the wafer map to determine failure patterns.

11. The method of claim 9, wherein the wafer map is generated by plyview.

12. The method of claim 8 wherein the objects tested include phase locked loops.

13. The method of claim 8 wherein the objects tested include embedded arrays.

14. The method of claim 8 wherein the objects tested include at least one of a programmable logic array, a content addressable memory, a core, a macro or a scan chain.

15. The method of claim 8 wherein step b) further comprises determining a dimension of each object.

16. The method of claim 8 wherein step b) further comprises determining an orientation of each object.

17. The method of claim 8 wherein the location is obtained from physical layout design data.

18. The method of claim 8 further comprising displaying the location and shape of the selected objects on a wafer map.

19. The method of claim 8 further comprising providing a one to one correspondence between an object and one or more failing latches in the test data.

20. The method of claim 8, comprising:

physically plotting the location and shape of the failed objects on a visual map of the integrated circuit.

21. A method of illustrating test data comprising:

a) providing a wafer with objects located thereon;

b) testing the objects to create test data;

c) linking the test data with locations of the objects; and

d) building a map visually illustrating locations and shapes of selected failed objects which are chosen based on the test data, wherein the selected failed objects failed the test.

22. The method of claim 21 further comprising:

determining locations of each of the objects on the wafer;

constructing polygons to enclose each of the objects; and

building a cross-reference map to link the locations of each of the objects to the polygons; and

step d) comprises

referring to the cross-reference map to determine location of objects.

23. The method of claim 22 further comprising displaying the polygons of the selected objects on the map.

24. The method of claim 21 wherein the map indicates a physical location of the selected object on the wafer.

25. The method of claim 21 wherein the map indicates a physical location of the selected objects on an integrated circuit.

26. The method of claim 21, wherein step d) comprises:

physically plotting the location and shape of the failed objects on the map.