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Method for rapid estimation of wire delays and capacitances based on placement of cells

  • US 6,931,610 B1
  • Filed: 05/12/2000
  • Issued: 08/16/2005
  • Est. Priority Date: 05/12/2000
  • Status: Expired due to Fees
First Claim
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1. A method of estimating capacitance of interconnection wires in an integrated circuit design comprising:

  • determining a rectangle bounding a group of pins whose capacitance is to be estimated;

    determining a direction of a spine for connecting the pins based on the bounding rectangle;

    connecting the pins to the spine to minimize a total length of the spine and connections, thereby forming a spine tree; and

    using the spine tree as a parameter for estimating a capacitance of the interconnection wires.

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