Method for rapid estimation of wire delays and capacitances based on placement of cells
First Claim
1. A method of estimating capacitance of interconnection wires in an integrated circuit design comprising:
- determining a rectangle bounding a group of pins whose capacitance is to be estimated;
determining a direction of a spine for connecting the pins based on the bounding rectangle;
connecting the pins to the spine to minimize a total length of the spine and connections, thereby forming a spine tree; and
using the spine tree as a parameter for estimating a capacitance of the interconnection wires.
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Accused Products
Abstract
A fast method of estimating capacitances and wire delays in an integrated circuit design is based on placement information such as that contained in a gate schematic net list from a logic synthesis tool. A simple tree topology called a spine tree is constructed to connect the pins of the net as an approximation of actual connections therein. Capacitance is extracted for this topology assuming a worst case scenario, and Elmore delays are computed for the wire delays based on the worst-case capacitances. The method takes linear time as a function of the number of pins in the net and is much faster than using a Steiner tree method in this context.
29 Citations
10 Claims
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1. A method of estimating capacitance of interconnection wires in an integrated circuit design comprising:
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determining a rectangle bounding a group of pins whose capacitance is to be estimated;
determining a direction of a spine for connecting the pins based on the bounding rectangle;
connecting the pins to the spine to minimize a total length of the spine and connections, thereby forming a spine tree; and
using the spine tree as a parameter for estimating a capacitance of the interconnection wires. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification