Method and apparatus for generation of validation tests

• US 6,931,629 B1
• Filed: 12/30/1999
• Issued: 08/16/2005
• Est. Priority Date: 12/30/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Goveas, Melvyn A., Yount, Charles R.
• Primary Examiner(s): Dam, Tuan
• Assistant Examiner(s): KENDALL, CHUCK O
• Application Number:
  US09/475,526
• Time in Patent Office: 2,056 Days
• Field of Search: 717124-144, 714/38, 714/30, 714/36, 714/138
• US Class Current: 717/126
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

A computer system and a computer-implemented method for generating test programs that satisfy at least one termination criterion. The computer system includes a hardware unit to transmit data. A processor is coupled to the hardware unit and to a storage device. The storage device has stored therein at least one algorithm and a plurality of routines. When the processor executes a routine(s), data is generated. The routine causes the processor to access an algorithm, generate a test program, and analyze a test program. A computer implemented method is also disclosed for generating test programs.

Claims

1. A validation test system comprising:

a test builder to generate test program populations to test the functionality of an integrated circuit (IC);

a test generator to translate the test program populations into an executable test;

a test analyzer to execute the test program populations; and

a feedback engine to build and update a population of test programs by generating an abstract syntax tree (AST) for each test program populations.

2. The system of claim 1, wherein the feedback engine determines whether a predetermined test program population threshold has been reached after a test program populations has been executed.

3. The system of claim 2, wherein the feedback engine generates one or more mutated ASTs if it is determined that the predetermined test program population threshold has been reached.

4. The system of claim 3, wherein the feedback engine generates a mutated AST by selecting a first AST, removing a segment of the first AST and inserting a replacement segment into the first AST.

5. The system of claim 3, wherein the feedback engine generates a mutated AST by selecting a first AST and a second AST and combining a segment of the first AST with a segment of the second AST.

6. A method comprising:

generating test program populations at a test builder to test the functionality of an integrated circuit (IC);

translating the test program populations into an executable test at a test generator;

executing the test program populations at a test analyzer; and

generating an abstract syntax tree (AST) for each of the test program populations at a feedback engine.

7. The method of claim 6 wherein generating the AST comprises the feedback engine building and updating a population of test programs.

8. The method of claim 7 further comprising the feedback engine determining whether a predetermined test program population threshold has been reached after a test program populations has been executed.

9. The method of claim 8 further comprising the feedback engine generating one or more mutated ASTs if it is determined that the predetermined test program population threshold has been reached.

10. The method of claim 9 further comprising the feedback engine:

generating a mutated AST by selecting a first AST;

removing a segment of the first AST; and

inserting a replacement segment into the first AST.

11. The method of claim 9 further comprising the feedback engine:

generating a mutated AST by selecting a first AST and a second AST; and

combining a segment of the first AST with a segment of the second AST.

12. An article of manufacture including one or more computer readable media that embody a program of instructions, wherein the program of instructions, when executed by a processing unit, causes the processing unit:

generate test program populations at a test builder to test the functionality of an integrated circuit (IC);

translate the test program populations into an executable test at a test generator;

execute the test program populations at a test analyzer; and

generate an abstract syntax tree (AST) for each of the test program populations at a feedback engine.

13. The article of manufacture of claim 12 wherein the program of instructions, when executed by a processing unit, further causes the feedback engine to generate the AST by building and updating a population of test programs.

14. The article of manufacture of claim 13 wherein the program of instructions, when executed by a processing unit, further causes the feedback engine to determine whether a predetermined test program population threshold has been reached after a test program populations has been executed.

15. The article of manufacture of claim 14 wherein the program of instructions, when executed by a processing unit, further causes the feedback engine to generate one or more mutated ASTs if it is determined that the predetermined test program population threshold has been reached.

16. The article of manufacture of claim 15 wherein the program of instructions, when executed by a processing unit, further causes the feedback engine to:

generate a mutated AST by selecting a first AST;

remove a segment of the first AST; and

insert a replacement segment into the first AST.

17. The article of manufacture of claim 15 wherein the program of instructions, when executed by a processing unit, further causes the feedback engine to:

generate a mutated AST by selecting a first AST and a second AST; and

combine a segment of the first AST with a segment of the second AST.