Integrated circuit device and method of manufacturing the same

• US 6,933,205 B2
• Filed: 11/18/2002
• Issued: 08/23/2005
• Est. Priority Date: 06/30/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okumura, Katsuya, Matsunaga, Noriaki, Hayasaka, Nobuo, Matsuo, Mie
• Primary Examiner(s): Pham, Hoai
• Assistant Examiner(s): Peralta, Ginette
• Application Number:
  US10/298,059
• Publication Number:
  US 20030067052A1
• Time in Patent Office: 1,009 Days
• Field of Search: 438/406, 438779-783, 438/957, 438/210, 438238-239, 438/243, 438253-254, 438/396, 438/479
• US Class Current: 438/406
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 μm, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.

Claims

1. A method of manufacturing an integrated circuit device, comprising:

forming an active element on the side of one main surface of a first substrate;

forming a passive element on the side of a first main surface of a second substrate; and

allowing a second main surface opposite to the first main surface of the second substrate to face the main surface of the first substrate so as to allow the active element and the passive element to be electrically connected to each other via an electrode extending through the second substrate.

2. The method of manufacturing an integrated circuit device according to claim 1, wherein said passive element is an inductor.

3. The method of manufacturing an integrated circuit device according to claim 2, wherein said inductor is selectively formed by a plating treatment.

4. The method of manufacturing an integrated circuit device according to claim 2, wherein said inductor is formed by patterning a metal foil.

5. The method of manufacturing an integrated circuit device according to claim 1, wherein said second substrate is formed of a semiconductor substrate having a resistivity higher than a resistivity of a semiconductor substrate constituting said first substrate.

6. The method of manufacturing an integrated circuit device according to claim 1, wherein said second substrate is formed of an insulating substrate.

7. The method of manufacturing an integrated circuit device according to claim 1, wherein said electrode extending through the second substrate is formed by loading a conductive material in a connecting hole formed in the second substrate.

8. The method of manufacturing an integrated circuit device according to claim 1, wherein said electrode extending through the second substrate is a projection-like electrode formed on the side of the main surface of said first substrate.

9. The method of manufacturing an integrated circuit device according to claim 1, wherein allowing the active element and the passive element to be electrically connected to each other includes electrically connecting the electrode extending through the second substrate to the active element via a bump provided between then main surface of the first substrate and the second main surface of the second substrate.

10. The method of manufacturing an integrated circuit device according to claim 1, further comprising loading an insulating material between the main surface of the first substrate and the second main surface of the second substrate.

11. The method of manufacturing an integrated circuit device according to claim 1, wherein no passive element is formed on the side of the second main surface of the second substrate.

12. The method of manufacturing an integrated circuit device according to claim 1, wherein forming the passive element includes forming the passive element on the first main surface of the second substrate.