Reference voltage generator for hysteresis circuit

• US 6,933,760 B2
• Filed: 09/19/2003
• Issued: 08/23/2005
• Est. Priority Date: 09/19/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Oh, Sooseok, Haider, Nazar Syed
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US10/666,508
• Publication Number:
  US 20050062522A1
• Time in Patent Office: 704 Days
• Field of Search: 327/206, 327/208, 327/210, 327/541, 327/543, 327407-413, 326/23, 326/24, 323/313, 323/314
• US Class Current: 327/206
• CPC Class Codes: G05F 1/465 Internal voltage generators for integrated circuits, e.g. step down generators

Abstract

A voltage reference generator for a hysteresis circuit, comprising a first originator circuit to generate a first reference voltage; a second originator circuit to generate a second reference voltage; and a selector circuit, coupled to the first and second originator circuits, to select one of the first and second reference voltages to be an output reference voltage based upon an input signal to the hysteresis circuit undertaking a low-to-high or a high-to-low signal transition respectively. The first originator circuit includes a first plurality of channel devices selected from either p-channel devices or n-channel devices and the second originator circuit includes a second plurality of channel devices selected from the other one of the p-channel devices and the n-channel devices.

Claims

1. A hysteresis circuit, comprising:

a sensing amplifier to generate an output signal having an output and two inputs with one of the inputs coupled to an input signal;

a reference generator coupled to the output and the other one of the inputs of the sensing amplifier and responsive to the output signal to generate an output reference voltage;

the reference generator including a first originator circuit to generate a first reference voltage on a first reference voltage node;

a second originator circuit to generate a second reference voltage on a second reference voltage node;

a selector circuit coupled to the first and second originator circuits to provide as the output reference voltage either the first or second reference voltage based upon the output signal undertaking a falling signal transition or a rising signal transition respectively;

a voltage supply; and

a ground;

the first originator circuit including a first p-channel device and a second p-channel device coupled in parallel between the voltage supply and the first reference voltage node; and

the second originator circuit including a first n-channel device and a second n-channel device coupled in parallel between the second reference voltage node and the ground.

2. The hysteresis circuit of claim 1, wherein the first originator circuit further includes a third p-channel device coupled between the first reference voltage node and the ground.

3. The hysteresis circuit of claim 2, wherein the second originator circuit further includes a third n-channel device coupled between the second reference voltage node and the voltage supply.

4. The hysteresis circuit of claim 3, wherein each of the p-channel and n-channel devices has a source, a drain and a gate;

the sources of the first and second p-channel devices are coupled to the voltage supply and the drains of the first and second p-channel devices are coupled to the first reference voltage node;

the source of the third p-channel device is coupled to the first reference voltage node and the drain of the third p-channel device is coupled to the ground;

the gate of the first p-channel device is coupled to the first reference voltage node; and

the gates of the second and third p-channel devices are coupled to the ground.

5. The hysteresis circuit of claim 4, wherein the drains of the first and second n-channel device are coupled to the second reference voltage node and the sources of the first and second n-channel devices are coupled to the ground;

the drain of the third n-channel device is coupled to the voltage supply and the source of the third n-channel device is coupled to the second reference voltage node;

the gates of the second and third n-channel devices are coupled to the voltage supply; and

the gate of the first n-channel device is coupled to the second reference voltage node.

6. The hysteresis circuit of claim 5, wherein the selector circuit is coupled between the first and second reference voltage nodes.

7. The hysteresis circuit of claim 5, wherein the reference voltage generator includes an output reference voltage node having the output reference voltage;

and the selector circuit includes a fourth p-channel device and a fourth n-channel device;

the fourth p-channel device has the drain coupled to the output reference voltage node and the source coupled to the first reference voltage node and the fourth n-channel device has the drain coupled to the output reference voltage node and the source coupled to the second reference voltage node.

8. The hysteresis circuit of claim 1, wherein the hysteresis circuit is included in an integrated circuit.

9. The hysteresis circuit of claim 8, wherein the integrated circuit is a microprocessor.

10. A system, comprising:

an integrated circuit having a reference generator to generate an output reference voltage;

a hysteresis circuit responsive to an input signal and the output reference voltage to generate an output signal;

the reference generator including a first originator circuit to generate a first reference voltage on a first reference voltage node;

a second originator circuit to generate a second reference voltage on a second reference voltage node;

a selector circuit coupled to the first and second originator circuits to provide as the output reference voltage either the first or second reference voltage based upon the output signal undertaking a falling signal transition or a rising signal transition respectively;

a voltage supply; and

a ground;

the first originator circuit including a first p-channel device and a second p-channel device coupled in parallel between the voltage supply and the first reference voltage node; and

the second originator circuit including a first n-channel device and a second n-channel device coupled in parallel between the second reference voltage node and the ground;

a DRAM coupled to the integrated circuit; and

an input/output interface coupled to the integrated circuit.

11. The system according to claim 10, the integrated circuit further includes a central processing unit, a main memory coupled to the central processor unit and at least one input/output module coupled to the central processor unit and the main memory.

12. The system of claim 10, wherein the first originator circuit further includes a third p-channel device coupled between the first reference voltage node and the ground.

13. The system of claim 12, wherein the second originator circuit further includes a third n-channel device coupled between the second reference voltage node and the voltage supply.

14. The system of claim 13, wherein each of the p-channel devices and n-channel devices has a source, a drain and a gate;

the sources of the first and second p-channel devices are coupled to the voltage supply and the drains of the first and second p-channel devices are coupled to the first reference voltage node;

the source of the third p-channel device is coupled to the first reference voltage node and the drain of the third p-channel device is coupled to the ground;

the gate of the first p-channel device is coupled to the first reference voltage node; and

the gates of the second and third p-channel devices are coupled to the ground.

15. The system of claim 14, wherein the drains of the first and second n-channel devices are coupled to the second reference voltage node and the sources of the first and second n-channel device are coupled to the ground;

the drain of the third n-channel device is coupled to the voltage supply and the source of the third n-channel device is coupled to the second reference voltage node;

the gates of the second and third n-channel devices are coupled to the voltage supply; and

the gate of the first n-channel device is coupled to the second reference voltage node.

16. The system of claim 15, wherein the selector circuit is coupled between the first and second reference voltage nodes.

17. The system of claim 15, wherein the reference voltage generator further includes an output reference voltage node having the output reference voltage;

and the selector circuit includes a fourth p-channel device an a fourth n-channel device;

the fourth p-channel device has the drain coupled to the output reference voltage node and the source coupled to the first reference voltage node and the fourth n-channel device has the drain coupled to the output reference voltage node and the source coupled to the second reference voltage node.

18. The system of claim 10, wherein the integrated circuit is a microprocessor.

19. The system of claim 10, wherein the input/output interface comprises a networking interface.

20. The system of claim 10, wherein the system is a selected one of a set-top box, an entertainment unit and a DVD player.