Non-volatile memory erase circuitry
First Claim
Patent Images
1. A non-volatile memory device comprising:
- an array of memory cells;
a counter circuit coupled to count voltage pulses applied to the memory cells and generate a count output in response to the counted voltage pulses; and
a voltage pump circuit for generating an elevated output voltage from an input voltage, the voltage pump circuit coupled to the counter circuit such that the elevated output voltage adjusts in response to the count output.
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Abstract
A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.
83 Citations
18 Claims
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1. A non-volatile memory device comprising:
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an array of memory cells;
a counter circuit coupled to count voltage pulses applied to the memory cells and generate a count output in response to the counted voltage pulses; and
a voltage pump circuit for generating an elevated output voltage from an input voltage, the voltage pump circuit coupled to the counter circuit such that the elevated output voltage adjusts in response to the count output. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A flash memory device comprising:
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an array of memory cells;
a first voltage pump coupled to produce an output voltage from an input voltage, wherein the output voltage is produced by sequentially elevating the input voltage through first series coupled pump stages;
a second voltage pump coupled in parallel to the first voltage pump to produce the output voltage from the input voltage, wherein the output voltage is produced by sequentially elevating the input voltage through second series coupled pump stages;
a counter for generating a count output comprising a quantity of voltage pulses applied to the array during memory operations; and
a control circuit coupled to the first and second voltage pumps and the counter, wherein the control circuit selectively activates, during the memory operations, the first and second voltage pumps in response to the count output. - View Dependent Claims (8)
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9. A flash memory device comprising:
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an array of memory cells; and
control circuitry for performing an erase operation on the memory cells, the control circuitry controlling a series of voltage pulses applied to the memory cells and adjusting a current limit of the voltage pulses in response to an input voltage pulse count indicative of a quantity of voltage pulses applied to the memory cells during memory operation. - View Dependent Claims (10)
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11. A method for erasing a flash memory device comprising:
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pre-programming a block of memory cells;
generating an erase voltage from a supply voltage using a voltage pump circuit having a plurality of parallel coupled pumps, the erase voltage being a multiple of the supply voltage;
applying a plurality of erase pulses to the block of memory cells, each erase pulse having a voltage level substantially equal to the erase voltage;
counting the erase pulses applied to the block of memory cells; and
adjusting a current limit of the erase voltage by selectively activating the plurality of parallel coupled pumps in response to an increasing count of the erase pulses. - View Dependent Claims (12, 13)
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14. A non-volatile memory system comprising:
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a processor that generates memory signals; and
a non-volatile memory device coupled to the processor, the memory device comprising;
an array of memory cells;
a counter circuit coupled to count voltage pulses applied to the memory cells, the counter circuit generating a count output in response to a quantity of voltage pulses; and
a voltage pump circuit for generating an elevated voltage output from an input voltage; and
control circuitry coupled to the voltage pump circuit for adjusting, during predetermined memory operations, a current sourced by the voltage pump circuit in response to the count output. - View Dependent Claims (15, 16, 17, 18)
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Specification