CMOS current mode RF detector and method

• US 6,934,520 B2
• Filed: 02/21/2002
• Issued: 08/23/2005
• Est. Priority Date: 02/21/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Rozsypal, Antonin
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): Jackson, Blane J.
• Application Number:
  US10/078,516
• Publication Number:
  US 20030157913A1
• Time in Patent Office: 1,279 Days
• Field of Search: 455/232.1, 455/234.1, 455/234.2, 455/245.1, 455/245.2, 455/127.1, 455/127.2, 455/126, 455/127.3, 330/288, 330/285, 330/130, 330/133, 330/134, 330/135, 330/138, 330277-279, 330/296, 330/221
• US Class Current: 455/127.3
• CPC Class Codes: G01R 21/01 in circuits having distributed constants G01R21/04, G01R21/07, G01R21/09, G01R21/12 take precedence
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 2001/0416 having gain or transmission power control

Abstract

An integrated detector circuit (20) includes first and second gain stages (GS₁, GS₂). The first gain stage has an input (82) that monitors a high frequency signal (V_RFDET) for routing a first detection current (IS₁) to a node (60). The second gain stage includes a first current source (PF₁) that supplies a bias current (I_MAX1) indicative of a predefined amplitude of the high frequency signal. An input of the second gain stage monitors the high frequency signal to route a portion of the bias current to the node as a second detection current (IS₂), which is limited to the bias current when the high frequency signal is greater than the predefined amplitude to compensate for a nonlinearity in a transconductance of the second gain stage.

Claims

1. An integrated detector circuit, comprising:

a first gain stage having an input that monitors a high frequency signal for routing a first detection current to a node and having a first current source coupled to form a first bias current having a first maximum value wherein a maximum value of the first detection current is limited to the first maximum value; and

a second gain stage including a second current source for supplying a second bias current having a second maximum value indicative of a predefined amplitude of the high frequency signal, and having an input for monitoring the high frequency signal to route a portion of the second bias current to the node as a second detection current, wherein the second detection current is limited to the second maximum value when the high frequency signal is greater than the predefined amplitude, and wherein the second maximum value is greater than the first maximum value.

2. An integrated detector circuit, comprising:

a first gain stage having an input that monitors a high frequency signal for routing a first detection current to a node; and

a second gain stage including a first current source for supplying a bias current indicative of a predefined amplitude of the high frequency signal, and having an input for monitoring the high frequency signal to route a portion of the bias current to the node as a second detection current, wherein the second detection current is limited to the bias current when the high frequency signal is greater than the predefined amplitude wherein the second gain stage includes a first transistor having a control electrode coupled for receiving the high frequency signal and a first conduction electrode coupled to the node for supplying the second detection current.

3. The integrated detector circuit of claim 2, wherein the current source includes a second transistor having a conduction electrode coupled to a second conduction electrode of the first transistor.

4. The integrated detector circuit of claim 3, wherein the first transistor is an n-channel metal oxide semiconductor field effect transistor (MOSFET) having a gate that functions as the control electrode and the second transistor is a p-channel MOSFET having a drain that functions as the conduction electrode.

5. The integrated detector circuit of claim 2, further comprising a third gain stage having an input that monitors the high frequency signal for routing a third detection current to the node.

6. The integrated detector circuit of claim 5, wherein the first gain stage includes:

a second current source for supplying a second bias current; and

a second transistor having a control electrode coupled for receiving the high frequency signal and a first conduction electrode for routing a portion of the second bias current to the node as the second detection current.

7. The integrated detector circuit of claim 6, wherein the first and second transistors are scaled to a ratio and the first and second detection currents are scaled to the ratio when the high frequency signal is zero.

8. The integrated detector circuit of claim 2, further comprising an amplifier having a first input coupled to receive a reference signal, a second input coupled to the node, and an output for maintaining the node at a predetermined potential.

9. The integrated detector circuit of claim 2, wherein the high frequency signal operates at a frequency greater than four hundred megahertz.

10. A detector circuit, comprising gain stages wherein each gain stage includes a current source for establishing maximum current levels in the gain stages at corresponding amplitudes of a high frequency signal and wherein each gain stage has a different maximum current level, wherein the gain stages function with transfer functions that convert the high frequency signal to detection currents for summing at a common node to produce an output detection signal as a substantially linear function of the high frequency signal, wherein the detection currents reach the maximum current levels at the corresponding amplitudes to compensate for nonlinearities in the transfer functions.

11. A detector circuit, comprising gain stages that include current sources for establishing maximum current levels in the gain stages at corresponding amplitudes of a high frequency signal, wherein the gain stages function with transfer functions that convert the high frequency signal to detection currents for summing at a common node to produce an output detection signal as a substantially linear function of the high frequency signal, wherein the detection currents reach the maximum current levels at the corresponding amplitudes to compensate for nonlinearities in the transfer functions and wherein the gain stages include transistors whose control electrodes are coupled to an input of the detector circuit and whose sources are coupled to the common node for providing the detection currents.

12. The detector circuit of claim 11, further comprising:

an amplifier having a first input for receiving a reference voltage and a second input coupled to the common node; and

a first transistor having a control electrode coupled to an output of the amplifier and a conduction electrode coupled to tho common node.

13. A method of detecting a high frequency signal, comprising the steps of:

amplifying a high frequency signal with a first transconductance to produce a first detection current;

amplifying the high frequency signal with a second transconductance to produce a second detection current for summing with the first detection current to produce an output signal; and

limiting the first detection current to a constant value to compensate for a nonlinearity in the second transconductance when the high frequency signal is greater than a predefined amplitude.

14. The method of claim 13, wherein the step of limiting includes the steps of:

generating a bias current with a current source; and

routing a portion of the bias current through a transistor with the high frequency signal to produce the first detection current.

15. The method of claim 13, further comprising the step of summing the first and second detection currents at a node to produce an output signal.

16. The method of claim 15, further comprising the steps of:

developing a reference voltage with a reference current; and

amplifying a difference between the reference voltage and a potential at the node to produce a correction signal that maintains the potential at the node substantially constant.

17. The method of claim 13, wherein the step of amplifying a high frequency signal with a first transconductance includes the step of converting a signal operating at a frequency greater than about four hundred megahertz to the first detection current.

18. A detector circuit, comprising:

a current source for providing a bias current;

a first transistor operating in response to a high frequency signal and having a first width and a first conduction electrode coupled to a node for producing a portion of the bias current as a first detection current; and

a second transistor operating in response to the high frequency signal, having a second width less than the first width, and having a first conduction electrode coupled to the node for producing a second detection current for summing with the first detection current to produce an output signal.

19. The detector circuit of claim 18, wherein the first detection current has a value substantially equal to the bias current when the high frequency signal is greater than a predefined amplitude to compensate for a nonlinearity in a transfer function of the second transistor.

20. The detector circuit of claim 19, further comprising a third transistor having a conduction electrode coupled to a second conduction electrode of the first transistor to supply the bias current.