Integrated circuit having integrated programmable gate array and method of operating the same

• US 6,934,597 B1
• Filed: 03/26/2002
• Issued: 08/23/2005
• Est. Priority Date: 03/26/2002
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Bemanian, Majid, Scharf, William D.
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): Lee, Douglas S.
• Application Number:
  US10/106,432
• Time in Patent Office: 1,246 Days
• Field of Search: 700/90, 700/121, 702/117, 702/121, 710/52, 710/62, 710/72, 709/230, 709/250, 714/725, 716/16, 716/17
• US Class Current: 700/121
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

Claims

1. An integrated circuit (IC), comprising:

at least two interfaces;

a programmable gate array (PGA) configured with at least a portion of a design during fabrication of said IC and coupled to said at least two interfaces for communicating data therebetween; and

an optional field-programmable gate array (FPGA) having a configuration memory associated therewith and coupled to and configured to cooperate with said PGA to adapt said IC to a particular surrounding environment.

2. The IC as recited in claim 1 further comprising a standard input-output interface.

3. The IC as recited in claim 1 further comprising a second standard input-output interface.

4. The IC as recited in claim 1 further comprising a double data rate interface.

5. The IC as recited in claim 1 further comprising a co-processor coupled to embedded memory.

6. The IC as recited in claim 1 wherein said at least two interfaces are selected from the group consisting of:

a system physical interface (SPI), and

a 10-Gigabit Attachment Unit Interface (XAUI).

7. The IC as recited in claim 1 further comprising a bus expander coupled to said PGA.

8. A method of manufacturing an integrated circuit (IC) suited for a particular application, comprising:

forming an integrated circuit having a substrate, at least two interfaces, an optional field-programmable gate array (FPGA) and a programmable gate array (PGA);

configuring said PGA during said manufacturing with at least a portion of a design; and

subsequently providing a configuration program to configure said FPGA to cooperate with said PGA to adapt said IC to a particular surrounding environment.

9. The method as recited in claim 8 further comprising forming a standard input-output interface on said substrate.

10. The method as recited in claim 8 further comprising forming a second standard input-output interface on said substrate.

11. The method as recited in claim 8 further comprising forming a double data rate interface on said substrate.

12. The method as recited in claim 8 further comprising forming a co-processor on said substrate.

13. The method as recited in claim 8 wherein said at least two interfaces are selected from the group consisting of:

a system physical interface (SPI), and

a 10-Gigabit Attachment Unit Interface (XAUI).

14. The method as recited in claim 8 further comprising forming a bus expander on said substrate.