Specifying and targeting portions of a graphical program for execution by multiple targets

• US 6,934,668 B2
• Filed: 05/09/2003
• Issued: 08/23/2005
• Est. Priority Date: 08/18/1997
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Butler, Cary P., Odom, Brian K., Andrade, Hugo
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US10/434,688
• Publication Number:
  US 20030195729A1
• Time in Patent Office: 837 Days
• Field of Search: 703/2, 703/22, 702/119, 702/119.57, 702/123, 702/127, 716/1, 716/16, 716/17, 716/18, 717/106, 717/125, 345/700, 345/771
• US Class Current: 703/2
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.

Claims

1. A memory medium which stores program instructions for configuring multiple targets to execute portions of a graphical program, wherein the targets include an embedded processor and memory, and a programmable hardware element, wherein the program instructions are executable to perform:

receiving user input selecting a first portion of the graphical program for execution on the programmable hardware element; and

generating first code based on the first portion of the graphical program that is deployable on the programmable hardware element; and

generating second code based on a second portion of the graphical program that is deployable on the embedded processor.

2. The memory medium of claim 1, wherein the graphical program comprises a model.

3. The memory medium of claim 1, wherein the graphical program comprises a plurality of interconnected nodes that visually represent functionality of a procedure.

4. The memory medium of claim 1, wherein the graphical program comprises a block diagram.

5. The memory medium of claim 1,

wherein the first portion of the graphical program requires a greater real-time response;

and

wherein the second portion of the graphical program requires a lesser real-time response.

6. The memory medium of claim 1, wherein generating further comprises establishing an inter-process communication link between the first portion of the graphical program and the second portion of the graphical program.

7. The memory medium of claim 1, wherein the second portion of the graphical is operable to receive output from the first portion of the graphical program, and process the output.

8. The memory medium of claim 7, wherein said processing the output comprises displaying the output on a computer display.

9. The memory medium of claim 1, wherein the program instructions are further executable to perform:

executing the first portion of the graphical program on the programmable hardware element; and

executing the second code on the embedded processor.

10. The memory medium of claim 1, wherein said receiving user input comprises receiving the user input through a graphical user interface (GUI).

11. The memory medium of claim 1, wherein the first code comprises an FPGA program file.

12. The memory medium of claim 11, wherein the program instructions further comprise a set of pre-defined instructions for generating the hardware description corresponding to the first portion of the graphical program.

13. The memory medium of claim 11, wherein the program instructions further comprise a compiler for compiling the hardware description for the programmable hardware element.

14. The memory medium of claim 1, wherein the first code comprises a hardware description.

15. The memory medium of claim 1, wherein the second portion of the graphical program comprises a remaining portion of the graphical program.

16. A system for configuring multiple targets to execute portions of a graphical program, wherein the targets include an embedded processor and memory, and a programmable hardware element, the system comprising:

means for receiving user input selecting a first portion of the graphical program for execution on the programmable hardware element; and

means for generating first code based on the first portion of the graphical program that is deployable on the programmable hardware element; and

means for generating second code based on a second portion of the graphical program that is deployable on the embedded processor.

17. A memory medium which stores program instructions for configuring multiple targets to execute portions of a graphical program, wherein the targets include an embedded processor and memory, and a programmable hardware element, wherein the program instructions are executable to perform:

storing the graphical program, wherein the graphical program comprises a plurality of interconnected nodes which visually indicate functionality of the graphical program;

generating first code based on a first portion of the graphical program that is deployable on the programmable hardware element; and

generating second code based on a second portion of the graphical program that is deployable on the embedded processor.

18. The memory medium of claim 17, wherein the targets further comprise a computer system, including a CPU and memory, and wherein the program instructions are further executable to perform:

receiving first user input selecting the first portion of the graphical program for execution on the programmable hardware element;

receiving second user input selecting the second portion of the graphical program for execution on the embedded processor; and

generating third code based on a third portion of the graphical program that is deployable on the computer system.

19. The memory medium of claim 18, wherein the program instructions are further executable to perform:

receiving third user input selecting the third portion of the graphical program for execution on the computer system.

20. The memory medium of claim 17, wherein the targets further comprise a computer system, including a CPU and memory;

wherein said receiving user input selecting portions comprises;

receiving user input selecting portions of the graphical program for respective execution on the embedded processor, on the programmable hardware element, and on the computer system; and

wherein said generating code that is deployable on the embedded processor and on the programmable hardware element comprises;

generating code that is deployable on the embedded processor, on the programmable hardware element, and on the computer system, respectively.

21. A memory medium which stores program instructions for configuring multiple targets to execute portions of a graphical program, wherein the targets include an embedded processor and memory, and a programmable hardware element, wherein the program instructions are executable to perform:

receiving user input selecting a first portion of the graphical program for execution on the embedded processor, and a second portion of the graphical program for execution on the programmable hardware element; and

generating first code based on the first portion of the graphical program that is deployable on the embedded processor; and

generating second code based on the second portion of the graphical program that is deployable on the programmable hardware element.

22. The memory medium of claim 21, wherein the second code comprises an FPGA program file.

23. The memory medium of claim 21, wherein the second code comprises a hardware description.

24. The memory medium of claim 21, wherein the program instructions are further executable to perform:

deploying the first code on the embedded processor; and

deploying the second code on the programmable hardware element.

25. The memory medium of claim 24, wherein the program instructions are further executable to perform:

invoking execution of the graphical program, wherein said execution comprises;

executing the first code on the embedded processor; and

executing the second code on the programmable hardware element.

26. The memory medium of claim 21, wherein the targets further comprise a computer system, including a CPU and memory, wherein the program instructions are further executable to perform:

generating third code, wherein the third code is operable to be stored in the memory of the computer system, and wherein the third code is executable by the CPU of the computer system.

27. The memory medium of claim 26, wherein the program instructions are further executable to perform:

deploying the first code on the embedded processor;

deploying the second code on the programmable hardware element; and

storing the third code in the memory of the computer system for execution by the CPU of the computer system.

28. The memory medium of claim 27, wherein the program instructions are further executable to perform:

invoking execution of the graphical program;

wherein said execution comprises;

executing the first code on the embedded processor;

executing the second code on the programmable hardware element; and

executing the third code in the memory of the computer system for execution by the CPU of the computer system.

29. A memory medium which stores program instructions for configuring multiple targets to execute portions of a graphical program, wherein the targets include an embedded processor and memory, and a programmable hardware element, wherein the program instructions are executable to perform:

storing the graphical program, wherein the graphical program comprises portions for respective execution on the embedded processor and on the programmable hardware element;

deploying the portions on the embedded processor and on the programmable hardware element, respectively.

30. A memory medium which stores program instructions for configuring multiple targets to execute portions of a graphical program, wherein the targets include an embedded processor and memory, a programmable hardware element, and a computer system, wherein the program instructions are executable to perform:

receiving user input selecting portions of the graphical program for respective execution on the embedded processor, on the programmable hardware element, and on the computer system; and

generating first code that is deployable on the embedded processor, second code that is deployable on the programmable hardware element, and third code that is deployable on the computer system;

wherein the first code, the second code, and the third code, are respectively based on respective ones of the selected portions of the graphical program.

31. A system for configuring multiple targets to execute portions of a graphical program, comprising:

a host computer, comprising a CPU and a memory;

one or more devices, coupled to the host computer, wherein the one or more devices comprises;

a programmable hardware element; and

an embedded processor and an embedded memory;

wherein the memory of the host computer stores program instructions which are executable to;

receive user input selecting a first portion of the graphical program for execution on the embedded processor, and a second portion of the graphical program for execution on the programmable hardware element;

generate first code based on the first portion of the graphical program that is deployable on the embedded processor; and

generate second code based on the second portion of the graphical program that is deployable on the programmable hardware element.

32. The system of claim 31, wherein the program instructions are executable to:

generate third code for execution on the host computer based on a remaining portion of the graphical program; and

store the third code in the memory of the host computer for execution by the CPU of the host computer.

33. The system of claim 31, wherein the second code comprises an FPGA program file.

34. The system of claim 31, wherein the second code comprises a hardware description.

35. The system of claim 31, wherein the one or more devices comprise:

a first device, coupled to the host computer, wherein the first device comprises the programmable hardware element; and

a second device, coupled to the host computer, wherein the second device comprises the embedded processor and the embedded memory.

36. A method comprising:

identifying portions of a model as being either critical to a real-time execution of the model or non-critical to a real-time execution of the model; and

generating code that is capable of real-time execution based on the critical portions of the model.