Clock generation and distribution in an emulation system

• US 6,934,674 B1
• Filed: 09/24/1999
• Issued: 08/23/2005
• Est. Priority Date: 09/24/1999
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG), Mentor Graphics Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Douezy, Francois, Reblewski, Frederic, Barbier, Jean
• Primary Examiner(s): Thomson, W
• Application Number:
  US09/404,923
• Time in Patent Office: 2,160 Days
• Field of Search: 703/28, 703/19, 703/27, 703/23
• US Class Current: 703/23
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.

Claims

1. A method for clock generation and distribution in an emulation system comprising:

generating a derived clock signal from a look up table, wherein an index to the look up table is generated by counting cycles of a base clock signal;

stopping emulation by stopping the base clock signal, wherein the index to the look up table is stopped at a stopping point in a clock cycle of the derived clock signal and the derived clock signal does not continue to a subsequent transition before stopping; and

resuming emulation by resuming the base clock signal, wherein the derived clock signal is resumed at the stopping point in the clock cycle of the derived clock signal.

2. The method of claim 1, wherein generating the derived clock signal further comprises:

accessing an entry in a look up table having an address corresponding to a number of clock cycles that have been counted; and

outputting a signal level in response to the entry accessed.

3. An emulation system comprising:

a plurality of emulation boards each having hardware to emulate one or more circuit designs;

means for interconnecting the plurality of emulation boards;

a clock generation circuit to stop and resume emulation of the one or more circuit designs comprising

a base clock generation circuit that generates a base clock signal of a first frequency, and

a derived clock generation circuit having

a frequency divider circuit coupled to receive the base clock signal,

a counter circuit coupled to receive an output of the frequency divider circuit, and

a look up table coupled to receive an output of the counter circuit, wherein the output of the counter circuit is used to index entries in the look up table, and further wherein the entries in the look up table indicate a signal level for a derived clock signal generated by the clock generation circuit, wherein when the base clock signal is stopped, the derived clock signal is stopped at a stopping point in a clock cycle of the derived clock signal without continuing to a subsequent transition of the derived clock signal, and the derived clock signal is resumed from the stopping point when the base clock signal is resumed.

4. The emulation system of claim 3, further comprising a plurality of additional clock generation circuits coupled in parallel to generate a plurality of additional derived clock signals.

5. The emulation system of claim 4, wherein the plurality of additional clock generation circuits each further comprise a selection circuit comprising a multiplexor coupled to receive the base clock signal and to receive an external clock signal from an external source, the multiplexor having an output coupled to a respective frequency divider circuit, wherein a select input of the multiplexor is provided by the external source.

6. The emulation system of claim 5, wherein the plurality of additional clock generation circuits each further comprise a frequency multiplier circuit that multiplies the external clock signal and provides a multiplied external clock signal to the multiplexor.

7. The emulation system of claim 3, wherein the derived clock signal is distributed to the plurality of emulation boards.

8. An apparatus for generating clock signals in an emulation system comprising:

means for generating a derived clock signal from a look up table, wherein an index to the look up table is generated by counting cycles of a base clock signal;

means for stopping emulation by stopping the base clock signal wherein the index to the look up table is stopped at a stopping point in a clock cycle of the derived clock signal and the derived clock signal does not continue to a subsequent transition before stopping; and

means for resuming emulation by resuming the bass clock signal, wherein the derived clock signal is resumed at the stopping point in the clock cycle of the derived clock signal.

9. The apparatus of claim 8, wherein the means for generating a derived clock signal further comprises:

means for accessing an entry in a look up table having an address corresponding to a number of clock cycles that have been counted; and

means for outputting a signal level in response to the entry accessed.