Hardware I/O control block structure for mirrored and non-mirrored data transfers

• US 6,934,771 B1
• Filed: 02/12/2004
• Issued: 08/23/2005
• Est. Priority Date: 01/16/2002
• Status: Expired due to Fees

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Young, B. Arlen
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): NGUYEN, TANH Q
• Application Number:
  US10/779,417
• Time in Patent Office: 558 Days
• Field of Search: 710/5, 710/20, 710/24, 710/39, 710/62, 710/64, 710/72, 710/74, 710 8- 10, 710/14, 714/1, 714/6, 707/204, 711/106, 711/114, 711/161, 711/162
• US Class Current: 710/5
• CPC Class Codes: G06F 11/2087 with a common controller
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99955 Archiving or backup

Abstract

A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Claims

1. A hardware I/O control block structure stored in a memory, said hardware I/O control block structure comprising:

one of a read command for a read transaction and a write command for a write transaction to be executed by a target device;

a sister hardware I/O control block field; and

a target identification field wherein upon said sister hardware I/O control block field containing a valid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a mirrored data transaction using said target device identified using information in said target identification field.

2. The hardware I/O control block structure stored in a memory as in claim 1 wherein said hardware I/O control block structure is one of a plurality of hardware I/O control block structures in said memory.

3. The hardware I/O control block structure stored in a memory as in claim 1 wherein upon said sister hardware I/O control block field containing an invalid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a non-mirrored data transaction.

4. The hardware I/O control block structure stored in a memory as in claim 1 wherein said valid value comprises a valid hardware I/O control block identification number.

5. The hardware I/O control block structure stored in a memory as in claim 3 wherein said invalid value comprises a null identification number.

6. The hardware I/O control block structure stored in a memory as in claim 1 wherein said mirrored data transaction comprises a read transaction.

7. The hardware I/O control block structure stored in a memory as in claim 1 wherein said mirrored data transaction comprises a write transaction.

8. A system comprising:

a host adapter;

a plurality of target devices coupled to said host adapter; and

a memory coupled to said host adapter, and said memory having stored therein a hardware I/O control block structure comprising;

one of a read command for a read transaction and a write command for a write transaction to be executed by a target device in said plurality of target devices;

a sister hardware I/O control block field; and

a target identification field wherein upon said sister hardware I/O control block field containing a valid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a mirrored data transaction using said target device, in said plurality of target devices, identified using information in said target identification field.

9. The system of claim 8 wherein said hardware I/O control block structure is one of a plurality of hardware I/O control block structures in said memory.

10. The system of claim 8 wherein upon said sister hardware I/O control block field containing an invalid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a non-mirrored data transaction.

11. The system as in claim 8 wherein said valid value comprises a valid hardware I/O control block identification number.

12. The system as in claim 10 wherein said invalid value comprises a null identification number.

13. The system as in claim 8 wherein said mirrored data transaction comprises a read transaction.

14. The system as in claim 8 wherein said mirrored data transaction comprises a write transaction.