Traffic controller using priority and burst control for reducing access latency

• US 6,934,820 B2
• Filed: 06/10/2002
• Issued: 08/23/2005
• Est. Priority Date: 04/29/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lasserre, Serge, d'Inverno, Dominique Benoît Jacques, Chauvel, Gérard
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US10/166,160
• Publication Number:
  US 20020194441A1
• Time in Patent Office: 1,170 Days
• Field of Search: 710/57, 711/105, 711/106, 711/157, 711/158, 365/222
• US Class Current: 711/157
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Claims

1. A memory traffic access controller responsive to a plurality of requests to access a memory, comprising:

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value; and

wherein a request to access the memory comprises a request to access the memory by a peripheral circuit; and

wherein the circuitry for changing the initial priority value to a different priority value is responsive to an amount of time that the request to access the memory by a peripheral circuit is pending.

3. The memory traffic access controller of claim 1 and further comprising:

circuitry for detecting that a received request to access the memory is a burst access request; and

conversion circuitry for converting the burst access request into a plurality of burst access requests.

4. The memory traffic access controller of claim 3 wherein the conversion circuitry converts the burst access request into a plurality of burst access requests if the burst access request is for a burst of data quantities S which exceeds a number of bytes B.

2. A memory traffic access controller responsive to a plurality of requests to access a memory, comprising:

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein a request to access the memory comprises a request to access the memory to perform a refresh of the memory; and

wherein the circuitry for changing the initial priority value to a different priority value is responsive to an amount of time that the request to access the memory to perform a refresh of the memory is pending.

5. A memory traffic access controller responsive to a plurality of requests to access a memory, comprising:

circuitry for associating, for each of the plurality of requests, an initial priority value corresnonding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of recquests having a highest priority value;

wherein the circuitry for selectively changing the initial priority value to a different priority value does not change the initial priority value if the request to access the memory is by a host processor.

6. A memory traffic access controller responsive to a plurality of requests to access a memory, comprising:

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein a request to access the memory comprises a request to access the memory for video data;

wherein a request to access the memory comprises a request to access the memory by a host processor; and

wherein the initial priority corresponding to the request to access the memory for video data is of a lower priority than the initial priority corresponding to the request to access the memory by the host processor.

7. A memory traffic access controller responsive to a plurality of recquests to access a memory, comprising:

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein a request to access the memory comprises a request to access the memory by a peripheral circuit;

wherein a request to access the memory comprises a request to access the memory by a host processor; and

wherein the initial priority corresponding to the request to access the memory by a peripheral circuit is of a lower priority than the initial priority corresponding to the request to access the memory by the host processor.

8. A memory traffic access controller responsive to a plurality of requests to access a memory, comprising:

circuitry for associating, for each of the plurity of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein a request to access the memory comprises a request to access the memory to perform a refresh of the memory;

wherein a request to access the memory comprises a request to access the memory by a host processor; and

wherein the initial priority corresponding to the request to access the memory to perform a refresh of the memory is of a lower priority than the initial priority corresponding to the request to access the memory by the host processor.

9. A memory traffic access controller responsive to a plurality of requests to access a memory, comprising:

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein a request to access the memory comprises a request to access the memory by a peripheral circuit;

wherein a request to access the memory comprises a request to access the memory to perform a refresh of the memory;

wherein a request to access the memory comprises a request to access the memory by a host processor;

wherein a request to access the memory comprises a request to access the memory for video data; and

wherein the initial priority corresponding to the request to access the memory by the host processor is higher than each of the initial priority corresponding to the request to access the memory by a peripheral circuit, the request to access the memory to perform a refresh of the memory, and the request to access the memory for video data.

10. The memory traffic access controller of claim 9:

wherein the initial priority corresponding to the request to access the memory by the host processor is higher than the initial priority corresponding to the request to access the memory by a peripheral circuit;

wherein the initial priority corresponding to the request to access the memory by a peripheral circuit is higher than the initial priority corresponding to the request to access the memory to perform a refresh of the memory; and

wherein the initial priority corresponding to the request to access the memory to perform a refresh of the memory is higher than the initial priority corresponding to the request to access the memory for video data.

11. A computing system, comprising:

a memory;

a memory traffic access controller responsive to a plurality of requests to access the memory, and comprising;

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein, for a request to access the memory that comprises a request to access the memory by a peripheral circuit, the circuitry for changing the initial priority value to a different priority value is responsive to an amount of time that the request to access the memory by a peripheral circuit is pending; and

wherein, for a request to access the memory comprising a request to access the memory to perform a refresh of the memory, the circuitry for changing the initial priority value to a different priority value is responsive to an amount of time that the request to access the memory to perform a refresh of the memory is pending.

12. A method of operating a memory traffic access controller responsive to a plurality of requests to access a memory, comprising the steps of:

associating, for each of the plurality of requests, an initial priority value corresponding to the request;

changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein a request to access the memory comprises a request to access the memory by a peripheral circuit; and

wherein the step of changing the initial priority value to a different priority value is responsive to an amount of time that the request to access the memory by a peripheral circuit is pending.

13. A method of operating a memory traffic access controller responsive to a plurality of requests to access a memory, comprising the steps of:

associating, for each of the plurality of requests, an initial priority value corresponding to the request;

changing the initial priority value for selected ones of the plurality of requests to a different priority value depending on the situation in the memory traffic access controller; and

outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein a request to access the memory comprises a request to access the memory to perform a refresh of the memory; and

wherein the step of changing the initial priority value to a different priority value is responsive to an amount of time that the request to access the memory to perform a refresh of the memory is pending.

14. A method of operating a memory traffic access controller responsive to a plurality of requests to access a memory, comprising the steps of:

associating, for each of the plurality of requests, an initial priority value corresponding to the request;

changing the initial priority value for selected ones of the plurality of recquests to a different priority value depending on the situation in the memory traffic access controller; and

outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value;

wherein the step of selectively changing the initial priority value to a different priority value does not change the initial priority value if the request to access the memory is by a host processor.

15. A memory traffic access controller responsive to a plurality of requests to access a memory, comprising:

circuitry for maintaining at least one row of said memory active for consecutive memory accesses;

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

16. The memory traffic access controller of claim 15, wherein said consecutive memory accesses are SDRAM accesses.

17. The memory traffic access controller of claim 15, further including a means for enabling and disabling said circuitry for maintaining at least one row of said memory active for consecutive memory accesses.

18. The memory traffic access controller of claim 15, further including a programmable bit for enabling and disabling said circuitry for maintaining at least one row of said memory active for consecutive memory accesses.

19. A computing system, comprising:

a memory;

a memory traffic access controller responsive to a plurality of requests to access the memory, and comprising;

circuitry for maintaining at least one row of said memory active for consecutive memory accesses;

circuitry for associating, for each of the plurality of requests, an initial priority value corresponding to the request;

circuitry for changing the initial priority value for selected ones of the plurality of requests to a different priority value; and

circuitry for outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

20. A method of operating a memory traffic access controller responsive to a plurality of requests to access a memory, comprising the steps of:

maintaining at least one row of said memory active for consecutive memory accesses;

associating, for each of the plurality of requests, an initial priority value corresponding to the request;

changing the initial priority value for selected ones of the plurality of requests to a different priority value; and

outputting a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.