High-performance, superscalar-based computer system with out-of-order instruction execution

• US 6,934,829 B2
• Filed: 10/31/2003
• Issued: 08/23/2005
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes, Wang, Sze-Shun, Nguyen, Le Trong, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Hagiwara, Yasuaki
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US10/697,257
• Publication Number:
  US 20040093483A1
• Time in Patent Office: 662 Days
• Field of Search: 712/23, 712/215, 712/219, 712/234, 712/245, 712/211, 711/125, 711/123
• US Class Current: 712/23
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 : Register renaming
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 : Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 : Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A superscalar microprocessor for processing instructions having a sequential program order, the microprocessor comprising:

an instruction buffer configured to buffer a plurality of instructions, including at least one conditional branch instruction;

a plurality of functional units configured to execute instructions, thereby generating result data;

a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units;

a resource identifying circuit configured to concurrently identify execution resources for a plurality of buffered instructions, the identified execution resources for each of the plurality of buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction,

wherein the resource identifying circuit is further configured to make a group of at least two and not more than a maximum number N of instructions concurrently available for execution, wherein the group includes up to N conditional branch instructions;

an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of the available instructions to the functional units for execution, based on availability of the identified execution resources for each instruction and without regard to the sequential program order; and

a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file.

2. The microprocessor of claim 1, further comprising:

bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for any one or more of the plurality of functional units via an alternate data path that bypasses the register file,

wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file.

3. The microprocessor of claim 1, further comprising an instruction fetch unit configured to fetch instructions from an instruction store according to the sequential program order and to transfer fetched instructions to the instruction buffer.

4. The microprocessor of claim 1, wherein the instruction fetch unit includes a branch prediction circuit configured to detect a conditional branch instruction among the fetched instructions and to generate a branch bias signal indicating whether the conditional branch is predicted to be taken or not taken.

5. The microprocessor of claim 4, wherein the instruction fetch unit is further configured to select an instruction to be transferred to the instruction buffer subsequent, in the sequential program order, to the conditional branch instruction based at least in part on the branch bias signal.

6. The microprocessor of claim 1, further comprising retirement control logic coupled to the register file and configured to concurrently retire a plurality of instructions according to the sequential program order.

7. The microprocessor of claim 1, wherein the resource identifying circuit is further configured to concurrently identify execution resources for a first one and a second one of the plurality of buffered instructions, wherein the second one of the instructions has a data dependency on the first one of the instructions.

8. A method for processing instructions having a sequential program order in a superscalar microprocessor, the method comprising:

buffering a plurality of instructions, including at least one conditional branch instruction;

concurrently identifying execution resources for more than one of a plurality of buffered instructions, the identified execution resources for each of the plurality of buffered instructions including a functional unit capable of executing the instruction arid a register file entry corresponding to a source of an operand for the instruction;

making a group of at least two and not more than a maximum number N of instructions for which execution resources have been identified concurrently available for execution, wherein the group includes up to N conditional branch instructions;

concurrently issuing more than one of the group of available instructions for execution by a plurality of functional units, based on availability of the identified execution resources for each instruction and without regard to the sequential program order;

executing the issued instructions in the plurality of functional units, thereby generating result data; and

transferring the result data from the functional units to a register file, the register file including a plurality of entries.

9. The method of claim 8, further comprising, concurrently with the act of transferring, bypassing the result data from a first one of the plurality of functional units as operand data for any one or more of the plurality of functional units.

10. The method of claim 8, further comprising fetching instructions from an instruction store according to the sequential program order.

11. The method of claim 10, further comprising:

detecting a conditional branch instruction among the fetched instructions; and

generating a branch bias signal indicating whether the conditional branch is predicted to be taken or not taken.

12. The method of claim 11, wherein the act of buffering a plurality of instructions includes selecting and buffering an instruction that is subsequent, in the sequential program order, to the conditional branch instruction, wherein the selection is based at least in part on the branch bias signal.

13. The method of claim 8, further comprising retiring instructions according to the sequential program order.

14. The method of claim 8, wherein concurrently identifying execution resources for more than one of the plurality of buffered instructions includes concurrently identifying execution resources for a first one and a second one of the plurality of buffered instructions, wherein the second one of the instructions has a data dependency on the first one of the instructions.

15. A computer system, comprising:

a memory;

a superscalar microprocessor for processing instructions having a sequential program order; and

a bus coupled between the memory and the microprocessor,

wherein the microprocessor includes;

an instruction buffer configured to buffer a plurality of instructions, including at least one conditional branch instruction;

a plurality of functional units configured to execute instructions, thereby generating result data;

a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units;

a resource identifying circuit configured to concurrently identify execution resources for a plurality of buffered instructions, the identified execution resources for each of the plurality of buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction,

wherein the resource identifying circuit is further configured to make a group of at least two and not more than a maximum number N of instructions concurrently available for execution, wherein the group includes up to N conditional branch instructions;

an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of the available instructions to the functional units for execution, based on availability of the identified execution resources for each instruction and without regard to the sequential program order; and

a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file.

16. The system of claim 15, wherein the microprocessor further includes:

bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for any one or more of the plurality of functional units via an alternate data path that bypasses the register file,

wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file.

17. The system of claim 15, wherein the microprocessor further includes an instruction fetch unit configured to fetch instructions from an instruction store according to the sequential program order and to transfer fetched instructions to the instruction buffer.

18. The system of claim 17, wherein the instruction fetch unit includes a branch prediction circuit configured to detect a conditional branch instruction among the fetched instructions and to generate a branch bias signal indicating whether the conditional branch is predicted to be taken or not taken.

19. The system of claim 18, wherein the instruction fetch unit is further configured to select an instruction to be transferred to the instruction buffer subsequent, in the sequential program order, to the conditional branch instruction based at least in part on the branch bias signal.

20. The computer system of claim 15, wherein the microprocessor further includes retirement control logic coupled to the register file and configured to concurrently retire a plurality of instructions according to the sequential program order.

21. The system of claim 15, wherein the resource identifying circuit is further configured to concurrently identify execution resources for a first one and a second one of the plurality of buffered instructions, wherein the second one of the instructions has a data dependency on the first one of the instructions.