Exception mechanism for a computer
First Claim
1. The computer, comprising:
- a multi-stage execution pipeline;
an instruction decoder designed;
to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline;
to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer, to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete;
the pipeline being designed to recognize an exception occurring in an instruction after an earlier side-effect of the instruction has been architecturally committed and before a later side of the instruction is architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler; and
pipeline resumption circuitry effective after completion of the software exception handler to resume execution of the excepted program based on the information in the processor registers;
the processor registers of the computer being designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory.
3 Assignments
0 Petitions
Accused Products
Abstract
A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers. The processor registers of the computer are designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory, the processor registers and general purpose registers of the computer together providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory.
341 Citations
71 Claims
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1. The computer, comprising:
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a multi-stage execution pipeline;
an instruction decoder designed;
to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline;
to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer, to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete;
the pipeline being designed to recognize an exception occurring in an instruction after an earlier side-effect of the instruction has been architecturally committed and before a later side of the instruction is architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler; and
pipeline resumption circuitry effective after completion of the software exception handler to resume execution of the excepted program based on the information in the processor registers;
the processor registers of the computer being designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory.
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2. The method, comprising the steps of:
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decoding and executing instructions of a complex instruction set of a computer, the instruction set having variable-length instructions and many instructions having multiple side-effects;
storing information describing the decoding of the complex instructions into architecturally-visible processor registers of the computer. - View Dependent Claims (3, 4, 5, 6, 7)
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8. The computer, comprising:
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an instruction decoder and pipeline designed to decode and execute instructions of a complex instruction set having variable-length instructions and many instructions having multiple side-effects;
processor register control circuitry designed to store information describing the decoding of the complex instructions into architecturally-visible processor registers of the computer. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. The method, comprising the steps of:
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executing a program in user state of a computer, the program coded in an instruction set having many instructions with multiple side-effects and the potential to raise multiple exceptions;
in response to recognizing an exception occurring in an instruction after an earlier side-effect of the instruction has been architecturally committed and before a later side-effect of the instruction is architecturally committed, transferring control to a software exception handler for the exception, and resuming execution of the excepted instruction after completion of the exception handler, processor registers of the computer being designed to architecturally expose sufficient information about the intermediate state of the excepted instruction that the transfer and resume are effected without saving intermediate results of the excepted instruction on a memory stack. - View Dependent Claims (22, 23, 24)
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25. The computer, comprising:
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an instruction decoder for an instruction set exposed for execution by user-state programs, many individual instructions of the instruction set having multiple side-effects and a potential to raise multiple exceptions;
pipeline control circuitry designed to recognize an exception occurring in an instruction after an earlier side-effect of the instruction has been architecturally committed and before a later side-effect of the instruction is architecturally committed, to transfer control to a software exception handler for the earlier exception, and to resume execution of the excepted instruction after completion of the exception handler, processor registers of the computer being designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving intermediate results of the excepted instruction on a memory stack. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. The method, comprising the step of:
while decoding a sequence of computer instructions for execution in a multi-stage execution pipeline and before commencing substantial execution of each decoded instruction of the sequence, generating information descriptive of the instruction, and, depending on a determination of whether the instruction will complete in the pipeline, storing or abstaining from storing the generated information into a non-pipelined register of the computer. - View Dependent Claims (36, 37)
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38. The computer, comprising:
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a multi-stage execution pipeline;
an instruction decoder designed to generate information descriptive of instructions to be executed by the pipeline, and to store the information into a non-pipelined register of the computer;
the instruction decoder being designed to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the register for instructions following an instruction determined not to complete. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45)
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46. The method, comprising the steps of:
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while executing a program coded in an instruction set exposed for execution by programs stored in a main memory of the computer, recognizing an exception occurring in a program, and in response, architecturally exposing in processor registers of the computer information describing a processor state of the computer and transferring execution to an exception handler;
after completion of the software exception handler, resuming execution of the excepted program based on the information in the processor registers;
the processor registers and general purpose registers of the computer architecturally exposing sufficient processor slate and providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory. - View Dependent Claims (47, 48)
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49. The computer, comprising:
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an instruction decoder for an instruction set exposed for execution by programs stored in a main memory of the computer, pipeline exception circuitry, effective on recognizing an exception occurring in a stored program, to architecturally expose in processor registers of the computer information describing a processor state of the computer, and to transfer execution to an exception handler; and
pipeline resumption circuitry effective after completion of the software exception handler to resume execution of the excepted program based on the information in the processor registers;
the processor registers and general purpose registers of the computer architecturally exposing sufficient processor state and providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. The method, comprising the steps of:
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fetching instructions in a first external instruction set from a memory, and, for at least some instructions of the first instruction set, issuing two or more instructions in a second form into an execution pipeline;
architecturally exposing an intra-instruction program counter value when an instruction of the first instruction set raises an exception at an intermediate point. - View Dependent Claims (60)
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61. The computer, comprising:
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an instruction decoder and execution pipeline, the decoder designed to fetch instructions in a first instruction set from a memory, and, for at least some instructions of the first instruction set, to issue two or more instructions in a second internal form into the execution pipeline;
a register and control logic for that register that capture and architecturally expose an intra-instruction program counter value when an instruction of the first instruction set raises an exception at an intermediate point. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71)
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Specification