Timing performance analysis
First Claim
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1. A method for performing a timing analysis for a core device to be embedded in a programmable logic device, comprising:
- obtaining clock-to-output timing information for the core device;
determining setup and hold timing information and delay timing information for a portion of the programmable logic device;
associating the clock-to-output timing information, the setup and hold timing information and the delay timing information with respective signals; and
calculating a path time delay for each of the respective signals.
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Abstract
Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.
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Citations
15 Claims
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1. A method for performing a timing analysis for a core device to be embedded in a programmable logic device, comprising:
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obtaining clock-to-output timing information for the core device; determining setup and hold timing information and delay timing information for a portion of the programmable logic device; associating the clock-to-output timing information, the setup and hold timing information and the delay timing information with respective signals; and calculating a path time delay for each of the respective signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for performing a timing analysis for a core device in a host integrated circuit, comprising:
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obtaining setup and hold timing information for the core device; determining clock-to-output timing information and delay timing information for a portion of the host integrated circuit; associating the clock-to-output timing information, the setup and hold timing information and the delay timing information with respective signals; calculating a path time delay for each of the respective signals; modifying the portion of the host integrated circuit in response to the path time delay for at least one of the respective signals being more than the clock period; determining circuitry values in response to modification of the portion of the host integrated circuit; and feeding back circuitry values and modifications of the portion of the host integrated circuit for re-determination of at least one of the clock-to-output timing information and the delay timing information for the portion of the host integrated circuit. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification