Timing performance analysis

• US 6,934,922 B1
• Filed: 02/27/2002
• Issued: 08/23/2005
• Est. Priority Date: 02/27/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Burnley, Richard P.
• Primary Examiner(s): Garbowski, Leigh M.
• Application Number:
  US10/084,515
• Time in Patent Office: 1,273 Days
• Field of Search: 716 1- 21
• US Class Current: 716/113
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.

Claims

1. A method for performing a timing analysis for a core device to be embedded in a programmable logic device, comprising:

obtaining clock-to-output timing information for the core device;

determining setup and hold timing information and delay timing information for a portion of the programmable logic device;

associating the clock-to-output timing information, the setup and hold timing information and the delay timing information with respective signals; and

calculating a path time delay for each of the respective signals.

2. The method of claim 1 further comprising determining whether the path time delay for each of the respective signals is less than a clock period.

3. The method of claim 2 further comprising modifying the portion of the programmable logic device in response to the path time delay for at least one of the respective signals being more than the clock period.

4. The method of claim 3 further comprising determining circuitry values in response to modification of the portion of the programmable logic device.

5. The method of claim 3 further comprising feeding back the circuitry values and modifications of the portion of the programmable logic device for re-determination of at least one of the setup and hold timing information and the delay timing information for the portion of the programmable logic device.

6. The method of claim 5 wherein the portion of the programmable logic device comprises logic and interconnects for coupling the core device to the programmable logic device.

7. The method of claim 6 wherein the portion of the programmable logic device comprises a memory controller coupled to the logic and interconnects.

8. The method of claim 7 wherein the core device is a microprocessor.

9. The method of claim 8 wherein the programmable logic device is a field programmable gate array.

10. A method for performing a timing analysis for a core device in a host integrated circuit, comprising:

obtaining setup and hold timing information for the core device;

determining clock-to-output timing information and delay timing information for a portion of the host integrated circuit;

associating the clock-to-output timing information, the setup and hold timing information and the delay timing information with respective signals;

calculating a path time delay for each of the respective signals;

modifying the portion of the host integrated circuit in response to the path time delay for at least one of the respective signals being more than the clock period;

determining circuitry values in response to modification of the portion of the host integrated circuit; and

feeding back circuitry values and modifications of the portion of the host integrated circuit for re-determination of at least one of the clock-to-output timing information and the delay timing information for the portion of the host integrated circuit.

11. The method of claim 10 further comprising determining whether the path time delay for each of the respective signals is less than a clock period.

12. The method of claim 10 wherein the portion of the host integrated circuit comprises logic and interconnects for coupling the core device to the host integrated circuit.

13. The method of claim 12 wherein the portion of the host integrated circuit comprises a memory controller coupled to the logic and interconnects.

14. The method of claim 13 wherein the core device is a microprocessor, and wherein the host integrated circuit is a programmable logic device.

15. The method of claim 14 wherein the programmable logic device is a field programmable gate array.