Process of fabricating a chip structure

• US 6,936,531 B2
• Filed: 10/20/2003
• Issued: 08/30/2005
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Chambliss, Alonzo
• Assistant Examiner(s): Brunson, M.
• Application Number:
  US10/690,250
• Publication Number:
  US 20040079966A1
• Time in Patent Office: 680 Days
• Field of Search: 438/26, 438/48, 438/106, 438/107, 438/110, 438611-614, 438622-625, 257/698, 257700-703, 257/723, 257/724, 257/758, 257/759, 257/774, 298/25, 298/29, 298/40, 298/54, 298/74
• US Class Current: 438/612
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. The process for fabricating a chip structure, comprising:

Step 1;

providing a wafer with a plurality of electric devices, an interconnection scheme and a passivation layer, the electric devices and the interconnection scheme arranged inside the wafer, the interconnection scheme electrically connected with the electric devices, the passivation layer disposed on a surface layer of the wafer, the passivation layer having at least one opening exposing the interconnection scheme, wherein the largest width of the opening of the passivation ranges from 0.5 microns to 20 microns;

Step 2;

forming a conductive layer over the passivation layer of the wafer, and the conductive layer electrically connected with the interconnection scheme;

Step 3;

forming a photoresist onto the conductive layer, and the photoresist having at least one opening exposing the conductive layer;

Step 4;

filling at least one conductive metal into the opening of the photoresist, and the conductive metal disposed over the conductive layer;

Step 5;

removing the photoresist; and

Step 6;

removing the conductive layer not covered with the conductive metal.

2. The process according to claim 1, wherein a dielectric sub-layer is formed over the passivation layer and covers the formed conductive metal after step 6 is performed.

3. The process according to claim 2, wherein at least one node opening is formed through the dielectric sub-layer to expose the conductive metal formed at a lower portion after the dielectric sub-layer is formed over the passivation layer and covers the formed conductive metal.

4. The process according to claim 2, wherein the dielectric sub-layer is made of an organic compound.

5. The process according to claim 2, wherein the dielectric sub-layer is made of a macramolecule polymer.

6. The process according to claim 2, wherein the dielectric sub-layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

7. The process according to claim 1, wherein the process further comprises:

Step 7;

forming a dielectric sub-layer over the passivation layer, the dielectric sub-layer covering the formed conductive metal, and the dielectric sub-layer having at least one opening exposing the conductive metal formed at a lower portion;

Step 8;

forming at least other one conductive layer on the dielectric sub-layer and into the opening of the dielectric sub-layer, and the other conductive layer electrically connected with the metal layer exposed by the opening of the dielectric sub-layer;

Step 9;

forming a photoresist onto the other conductive layer, and the photoresist having at least one opening exposing the other conductive layer;

Step 10;

filling at least other one conductive metal into the opening of the photoresist, and the other conductive metal disposed over the other conductive layer;

Step 11;

removing the photoresist; and

Step 12;

removing the other conductive layer not covered with the other conductive metal.

8. The process according to claim 7, wherein the dielectric sub-layer is made of an organic compound.

9. The process according to claim 7, wherein the dielectric sub-layer is made of a macramolecule polymer.

10. The process according to claim 7, wherein the dielectric sub-layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

11. The process according to claim 7, wherein the thickness of the dielectric sub-layer ranges from 1 micron to 100 microns.

12. The process according to claim 7, wherein at least other one dielectric sub-layer is formed over the passivation layer and covers the formed conductive metal after the step 12 is performed.

13. The process according to claim 12, wherein at least one node opening is formed through the other dielectric sub-layer to expose the conductive metal formed at a lower portion after the other dielectric sub-layer is formed over the passivation layer and covers the farmed conductive metal.

14. The process according to claim 12, wherein the other dielectric sub-layer is made of an organic compound.

15. The process according to claim 12, wherein the other dielectric sub-layer is made of a macromolecule polymer.

16. The process according to claim 12, wherein the other dielectric sub-layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

17. The process according to claim 7, wherein the sequential steps 7-12 are repeated at least one time.

18. The process according to claim 17, wherein at least other one dielectric sub-layer is formed over the passivation layer and covers the formed conductive metal after the sequential steps 7-12 are repeated at least one time.

19. The process according to claim 18, wherein at least one node opening is fanned through the other dielectric sub-layer to expose the conductive metal formed at a lower portion after the other dielectric sub-layer is formed over the passivation layer and covers the fanned conductive metal.

20. The process according to claim 18, wherein the other dielectric sub-layer is made of an organic compound.

21. The process according to claim 18, wherein the other dielectric sub-layer is made of a macromolecule polymer.

22. The process according to claim 18, wherein the other dielectric sub-layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, or elastomer.

23. The process according to claim 1, wherein the thickness of the trace constructed of the conductive layer and the conductive metal ranges from 1 micron to 50 microns.

24. The process according to claim 1, wherein the width of the trace constructed of the conductive layer and the conductive metal ranges from 1 micron to 1 centimeter.

25. The process according to claim 1, wherein the cross-sectional area of the trace constructed of the conductive layer and the conductive metal ranges from 1 square micron to 0.5 square millimeters.

26. The process according to claim 1, wherein the passivation layer is constructed of an inorganic compound.

27. The process according to claim 1, wherein the passivation layer is constructed of a silicon oxide compound, a silicon nitride compound, phosphosilicate glass (PSG), a silicon oxide nitride compound or a composite formed by laminating the above material.

28. The process according to claim 1, wherein, before the step 2 is performed, a dielectric sub-layer is formed on the passivation layer, the dielectric sub-layer includes at least one via metal opening connecting with the opening of the passivation layer, and, then, when the step 2 is performed, the conductive layer is formed on the dielectric sub-layer, the side wall of the via metal opening, and the interconnection scheme exposed by the opening of the passivation layer.

29. The process according to claim 28, wherein the largest width of the via metal opening is larger than that of the opening of the passivation.

30. The process according to claim 28, wherein the cross-sectional area of the via metal opening ranges from 1 square micron to 10,000 square microns.

31. The process according to claim 1, wherein during the step 2, a sputtering process is used to form the conductive layer over the passivation layer of the wafer.

32. The process according to claim 1, wherein during the step 4, an electroplating process is used to fill the conductive metal over the conductive layer.

33. The process according to claim 1, wherein the material of the conductive layer includes titanium-tungsten alloy, titanium or chromium.

34. The process according to claim 1, wherein the material of the conductive metal includes copper, nickel, or gold.