Process of fabricating a chip structure
First Claim
1. The process for fabricating a chip structure, comprising:
- Step 1;
providing a wafer with a plurality of electric devices, an interconnection scheme and a passivation layer, the electric devices and the interconnection scheme arranged inside the wafer, the interconnection scheme electrically connected with the electric devices, the passivation layer disposed on a surface layer of the wafer, the passivation layer having at least one opening exposing the interconnection scheme, wherein the largest width of the opening of the passivation ranges from 0.5 microns to 20 microns;
Step 2;
forming a conductive layer over the passivation layer of the wafer, and the conductive layer electrically connected with the interconnection scheme;
Step 3;
forming a photoresist onto the conductive layer, and the photoresist having at least one opening exposing the conductive layer;
Step 4;
filling at least one conductive metal into the opening of the photoresist, and the conductive metal disposed over the conductive layer;
Step 5;
removing the photoresist; and
Step 6;
removing the conductive layer not covered with the conductive metal.
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Accused Products
Abstract
A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
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Citations
34 Claims
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1. The process for fabricating a chip structure, comprising:
-
Step 1;
providing a wafer with a plurality of electric devices, an interconnection scheme and a passivation layer, the electric devices and the interconnection scheme arranged inside the wafer, the interconnection scheme electrically connected with the electric devices, the passivation layer disposed on a surface layer of the wafer, the passivation layer having at least one opening exposing the interconnection scheme, wherein the largest width of the opening of the passivation ranges from 0.5 microns to 20 microns;
Step 2;
forming a conductive layer over the passivation layer of the wafer, and the conductive layer electrically connected with the interconnection scheme;
Step 3;
forming a photoresist onto the conductive layer, and the photoresist having at least one opening exposing the conductive layer;
Step 4;
filling at least one conductive metal into the opening of the photoresist, and the conductive metal disposed over the conductive layer;
Step 5;
removing the photoresist; and
Step 6;
removing the conductive layer not covered with the conductive metal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification