Edge termination in MOS transistors

• US 6,936,890 B2
• Filed: 09/06/2002
• Issued: 08/30/2005
• Est. Priority Date: 09/13/2001
• Status: Expired due to Term

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hijzen, Erwin A., Hueting, Raymond J. E., In't Zandt, Michael A. A.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): VESPERMAN, WILLIAM C
• Application Number:
  US10/236,175
• Publication Number:
  US 20030047776A1
• Time in Patent Office: 1,089 Days
• Field of Search: 257/329, 257/330, 257/333, 257/339, 257/341, 257/471, 257/476, 257/488
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles:

• the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and
• a compatible 2D edge termination scheme is provided around the RESURF active device area.

These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

Claims

1. A semiconductor device comprises:

a semiconductor body having an active cell area wherein trenches containing gate material extend into the semiconductor body from a surface thereof, and wherein adjacent to each trench gate there is a source region at said semiconductor body surface;

the semiconductor body also having an inactive cell area wherein trenches containing gate material extend into the semiconductor body from the surface thereof, and wherein the source region is not present;

characterised in that a gate bondpad at least partially overlies the active cell area, or an area substantially surrounded by the active cell area, and is connected thereto.

2. A semiconductor device as claimed in claim 1, in which the gate bondpad overlies and is located substantially entirely within the active cell area.

3. A semiconductor device as claimed in claim 2, in which a subsidiary inactive cell area is located beneath the gate bondpad, and is contained within the active cell area.

4. A semiconductor device as claimed in claim 1, in which the perimeter of the device includes a termination area.

5. A semiconductor device as claimed in claim 4, in which the edge termination area is a trench network, forming a non-floating p-type or n-type implant.

6. A semiconductor device as claimed in claim 4, in which the edge termination area comprises at least one floating poly-silicon spacer used as a field plate.

7. A semiconductor device as claimed in claim 4, in which the edge termination area comprises a field plate on dielectric material in a perimeter trench, which dielectric material forms a thicker dielectric layer than a dielectric layer on said gate material in the active cell area.

8. A semiconductor device as claimed in claim 4, in which the edge termination area is constructed according to a Kao ring scheme.

9. A semiconductor device as claimed in claim 4, in which the edge termination area is constructed according to known 2D edge termination schemes.

10. A semiconductor device as claimed in claim 1, in which cells in the active area are surrounded by a plurality of substantially concentric ring trenches.

11. A semiconductor device as claimed in claim 10, in which the ring trenches are substantially circular or are substantially elliptical.

12. A semiconductor device as claimed in claim 10, in which the ring trenches are substantially polygonal, for example square ring trenches, rectangular ring trenches or hexagonal ring trenches.

13. A semiconductor device as claimed in claim 10, in which a plurality of cells have a common set of outer concentric ring trenches.

14. A semiconductor device as claimed in claim 10, in which the ring trenches have different widths.

15. A semiconductor device as claimed in claim 10, in which the cells are joined to a common gate bondpad.

16. A semiconductor device as claimed in any one of the preceding claims, in which the trenches in the active and inactive cell areas are sufficiently closely spaced (sufficiently small pitch) that intermediate areas of the drain drift region are depleted in a blocking condition of the device.