ESD protection device

• US 6,936,895 B2
• Filed: 10/09/2003
• Issued: 08/30/2005
• Est. Priority Date: 10/09/2003
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Agilent Technologies, Inc., Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Manna, Indrajit, Filippi, Raymond, Lo, Keng Foo, Tan, Pee Ya
• Primary Examiner(s): Kielin, Erik
• Assistant Examiner(s): DOTY, HEATHER ANNE
• Application Number:
  US10/682,055
• Publication Number:
  US 20050077577A1
• Time in Patent Office: 691 Days
• Field of Search: 438/237, 438/514, 438/517, 438/519, 438/527, 257/355, 257/656
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

Claims

1. A method to form an integrated circuit device comprising:

forming a dielectric layer overlying a semiconductor substrate;

forming an intrinsic semiconductor layer overlying said dielectric layer;

patterning said intrinsic semiconductor layer;

forming a p+ region in said intrinsic semiconductor layer;

forming an n+ region in said intrinsic semiconductor layer wherein said p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device; and

forming a source region and a drain region in said semiconductor substrate to thereby complete a MOSFET device wherein said PIN diode device is a gate electrode for said MOSFET device.

2. The method according to claim 1 wherein said dielectric layer comprises an oxide.

3. The method according to claim 1 wherein said semiconductor layer comprises polysilicon.

4. The method according to claim 1 wherein said semiconductor layer comprises amorphous silicon.

5. The method according to claim 1 wherein step of forming said p+ region comprises implanting ions and wherein a masking layer is used to control where said ions are implanted.

6. The method according to claim 1 wherein said step of forming said n+ region comprises implanting ions and wherein a masking layer is used to control where said ions are implanted.

7. The method according to claim 6 wherein said step of forming said source and drain regions comprises implanting ions and wherein said step is simultaneous with said step of forming said n+ region.

8. The method according to claim 1 further comprising:

forming spacers on the sidewalls of said PIN diode device;

forming a masking layer covering said intrinsic region

while exposing said p+ region, said n+ region, said source region, and said drain region;

depositing a metal layer overlying said source region, drain region, said n+ region, said p+ regions, said spacers, and said masking layer;

annealing said metal layer to form metal silicide regions overlying said source region, said drain region, said n+ region, and said p+ region; and

removing unreacted said metal layer.

9. The method according to claim 1 wherein said drain region and said p+ region are connected together to form a first terminal and wherein said source region and said n+ region are connected together to form a second terminal.

10. The method according to claim 9 wherein said first terminal is connected to a signal pad and said second terminal is connected to a ground pad.

11. The method according to claim 1 wherein said p+ region is a first terminal, wherein said drain region and said n+ region are connected together, and wherein said source region forms a second terminal.

12. The method according to claim 11 wherein said first terminal is connected to a signal pad and said second terminal is connected to a ground pad.

13. An integrated circuit device comprising:

a dielectric layer overlying a semiconductor substrate;

a PIN diode device overlying said dielectric layer wherein said PIN diode device comprises a semiconductor layer having a p+ region and an n+ region that are laterally separated by an intrinsic region; and

a MOSFET device comprising a source region and a drain region in said semiconductor substrate wherein said PIN diode device is a gate electrode for said MOSFET device.

14. The device according to claim 13 wherein said dielectric layer comprises an oxide.

15. The device according to claim 13 wherein said semiconductor layer comprises polysilicon.

16. The device according to claim 13 further comprising:

spacers on the sidewalls of said PIN diode device; and

metal silicide regions overlying said source region, said drain region, said n+ region, and said p+ region.

17. The device according to claim 13 wherein said drain region and said p+ region are connected together to form a first terminal and wherein said source region and said n+ region are connected together to form a second terminal.

18. The device according to claim 17 wherein said first terminal is connected to a signal pad and said second terminal is connected to a ground pad.

19. The device according to claim 13 wherein said p+ region is a first terminal, wherein said drain region and said n+ region are connected together, and wherein said source region forms a second terminal.

20. The device according to claim 19 wherein said first terminal is connected to a signal pad and said second terminal is connected to a ground pad.

21. An ESD protection device comprising:

a dielectric layer overlying a semiconductor substrate;

a PIN diode device overlying said dielectric layer wherein said PIN diode device comprises a semiconductor layer having a p+ region and an n+ region that are laterally separated by an intrinsic region; and

a MOSFET device comprising a source region and a drain region in said semiconductor substrate, wherein said PIN diode device is a gate electrode for said MOSFET device, wherein said drain region and said p+ region are connected together to form a first terminal, and wherein said source region and said n+ region are connected together to form a second terminal.

22. The device according to claim 21 wherein said dielectric layer comprises an oxide.

23. The device according to claim 21 wherein said semiconductor layer comprises polysilicon.

24. The device according to claim 21 further comprising:

spacers on the sidewalls of said PIN diode device; and

metal silicide regions overlying said source region, said drain region, said n+ region, and said p+ region.

25. The device according to claim 24 wherein said first terminal is connected to a signal pad and said second terminal is connected to a ground pad.

26. An ESD protection device comprising:

a dielectric layer overlying a semiconductor substrate;

a PIN diode device overlying said dielectric layer wherein said PIN diode device comprises a semiconductor layer having a p+ region and an n+ region that are laterally separated by an intrinsic region; and

a MOSFET device comprising a source region and a drain region in said semiconductor substrate, wherein said PIN diode device is a gate electrode for said MOSFET device, wherein said p+ region forms a first terminal, wherein said drain region and said n+ region are connected together, and wherein said source regions forms a second terminal.

27. The device according to claim 26 wherein said dielectric layer comprises an oxide.

28. The device according to claim 26 wherein said semiconductor layer comprises polysilicon.

29. The device according to claim 26 further comprising:

spacers on the sidewalls of said PIN diode device; and

metal silicide regions overlying said source region, said drain region, said n+ region, and said p+ region.

30. The device according to claim 26 wherein said first terminal is connected a signal pad and said second terminal is connected to a ground pad.

31. An ESD protection device comprising:

a dielectric layer overlying a semiconductor substrate;

a plurality of PIN diode devices overlying said dielectric layer wherein each said PIN diode device comprises a semiconductor layer having a p+ region and an n+ region that are laterally separated by an intrinsic region and wherein said PIN diode devices are in series; and

a MOSFET device comprising a source region and a drain region in said semiconductor substrate, wherein said PIN diode device is a gate electrode for said MOSFET device, wherein said drain region and said p+ of a first said PIN diode device are connected together to form a first terminal, and wherein said source region and said n+ region of a second said PIN diode device are connected together to form a second terminal.

32. The device according to claim 31 further comprising:

spacers on the sidewalls of said PIN diode device; and

metal silicide regions overlying said source region, said drain region, said n+ region, and said p+ region.

33. The device according to claim 31 wherein said first terminal is connected to a signal pad and said second terminal is connected to a ground pad.