Gate dielectric antifuse circuit to protect a high-voltage transistor

• US 6,936,909 B2
• Filed: 08/29/2002
• Issued: 08/30/2005
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Porter, John D., Marr, Kenneth W.
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US10/230,928
• Publication Number:
  US 20040041167A1
• Time in Patent Office: 1,097 Days
• Field of Search: 257/50, 257/530
• US Class Current: 257/530
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

Claims

1. An antifuse circuit comprising:

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit;

a high-voltage transistor comprising a first terminal coupled to the second terminal of the antifuse and a gate terminal to control the high-voltage transistor; and

a gate bias circuit coupled between the gate terminal of the high-voltage transistor, the first terminal of the antifuse, and a supply voltage to couple the gate terminal of the high-voltage transistor to an intermediate voltage between the supply voltage and the elevated voltage on the first terminal of the antifuse to protect the high-voltage transistor,

wherein the gate bias circuit further comprises;

a first adjustable resistor and a diode-connected transistor coupled in series between a common bus line and the gate terminal of the high-voltage transistor; and

a second adjustable resistor coupled between the gate terminal of the high-voltage transistor and the supply voltage.

2. The antifuse circuit of claim 1 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a read voltage during an active mode of operation; and

the antifuse circuit further comprises an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor and a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode.

3. The antifuse circuit of claim 1 wherein the high-voltage transistor further comprises:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising a drain coupled to the n-type well;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

4. An antifuse circuit comprising:

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit;

a high-voltage transistor comprising a first terminal coupled to the second terminal of the antifuse and a gate terminal to control the high-voltage transistor; and

a gate bias circuit to couple the gate terminal of the high-voltage transistor to an intermediate voltage between a supply voltage and the elevated voltage to protect the high-voltage transistor, the gate bias circuit comprising;

a first impedance coupled between the gate terminal of the high-voltage transistor and the first terminal of the antifuse;

a second impedance coupled between the gate terminal of the high-voltage transistor and the supply voltages;

a first adjustable resistor and a diode-connected transistor coupled in series between a common bus line and the gate terminal of the high-voltage transistor; and

a second adjustable resistor coupled between the sate terminal of the high-voltage transistor and the supply voltage.

5. The antifuse circuit of claim 4 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a read voltage during an active mode of operation; and

the antifuse circuit further comprises an n-channel transistor coupled to the source of the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor and a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode.

6. The antifuse circuit of claim 4 wherein the high-voltage transistor further comprises:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising a drain coupled to the n-type well;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

7. A memory device comprising:

an array of memory cells in an integrated circuit;

an address decoder coupled to the array in the integrated circuit;

a plurality of input/output paths coupled to an input/output control circuit coupled to the array in the integrated circuit; and

an antifuse circuit coupled to the array in the integrated circuit, the antifuse circuit comprising;

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal;

a high-voltage transistor comprising a first terminal coupled to the second terminal of the antifuse and a gate terminal to control the high-voltage transistor; and

a gate bias circuit coupled between the gate terminal of the high-voltage transistor, the first terminal of the antifuse, and a supply voltage to couple the gate terminal of the high-voltage transistor to an intermediate voltage between the supply voltage and the elevated voltage to protect the high-voltage transistor,

wherein the sate bias circuit further comprises;

a first adjustable resistor and a diode-connected transistor coupled in series between a common bus line and the gate terminal of the high-voltage transistor; and

a second adjustable resistor coupled between the gate terminal of the high-voltage transistor and the supply voltage.

8. The memory device of claim 7 wherein:

the integrated circuit further comprises a plurality of antifuses in banks of antifuses, each bank comprising a gate bias circuit and a plurality of the antifuses;

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a read voltage during an active mode of operation; and

the antifuse circuit further comprises an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor and a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode.

9. The memory device of claim 7 wherein the high-voltage transistor further comprises:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising a drain coupled to the n-type well;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide aver the substrate; and

a gate electrode over the layer of oxide.

10. A memory device comprising:

an array of memory cells in a memory device;

an address decoder coupled to the array in the memory device to decode address signals to access the memory cells;

a plurality of input/output paths coupled to the array to couple data to the memory cells;

an input/output control circuit coupled to the array in the memory device to control the data based on control signals;

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit in the memory device;

a high-voltage transistor comprising a first terminal coupled to the second terminal of the antifuse and a gate terminal to control the high-voltage transistor; and

a gate bias circuit coupled between the gate terminal of the high-voltage transistor, the first terminal of the antifuse, and a supply voltage to couple the gate terminal of the high-voltage transistor to an intermediate voltage between the supply voltage and the elevated voltage on the first terminal of the antifuse to protect the high-voltage transistor, wherein the gate bias circuit further comprises;

a first adjustable resistor and a diode-connected transistor coupled in series between a common bus line and the rate terminal of the high-voltage transistor; and

a second adjustable resistor coupled between the gate terminal of the high-voltage transistor and the supply voltage.

11. The memory device of claim 10 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a read voltage during an active mode of operation; and

the antifuse circuit further comprises an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor and a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode.

12. The memory device of claim 10 wherein the high-voltage transistor further comprises:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising a drain coupled to the n-type well;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

13. The memory device of claim 10 wherein the memory device comprises a static random access memory device.

14. The memory device of claim 10 wherein:

the input/output control circuit is coupled to receive a write enable signal, an output enable signal, and a chip enable signal to control the data; and

further comprising a power down circuit in the memory device coupled to the array to control the memory device during a power-down mode.

15. A system comprising:

a processor;

a memory system coupled to the processor;

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit in the memory system;

a high-voltage transistor comprising a first terminal coupled to the second terminal of the antifuse and a gate terminal to control the high-voltage transistor; and

a gate bias circuit coupled between the gate terminal of the high-voltage transistor, the first terminal of the antifuse, and a supply voltage to couple the gate terminal of the high-voltage transistor to an intermediate voltage between the supply voltage and the elevated voltage on the first terminal of the antifuse to protect the high-voltage transistor, wherein the gate bias circuit further comprises;

a first adjustable resistor and a diode-connected transistor coupled in series between a common bus line and the gate terminal of the high-voltage transistor; and

a second adjustable resistor coupled between the gate terminal of the high-voltage transistor and the supply voltage.

16. The system of claim 15 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a read voltage during an active mode of operation; and

the antifuse circuit further comprises an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor and a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode.

17. The system of claim 15 wherein the high-voltage transistor further comprises:

an n-type well in a p-type substrate;

an n+-type drain diffusion region in the well comprising a drain coupled to the n-type well;

an n+-type source diffusion region in the substrate comprising a source;

a layer of oxide over the substrate; and

a gate electrode over the layer of oxide.

18. The system of claim 15 further comprising:

a display unit;

an input/output subsystem; and

a bus coupled to the processor, the memory system, the display unit, and the input/output subsystem.

19. The system of claim 15 wherein the processor comprises a microprocessor.

20. An antifuse circuit comprising:

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit;

a high-voltage transistor comprising a first terminal coupled to the second terminal of the antifuse, a gate terminal to control the high-voltage transistor, and a second terminal;

a transistor coupled to the second terminal of the high-voltage transistor to control current flow through the antifuse and the high-voltage transistor;

a read circuit coupled to the high-voltage transistor to read the antifuse; and

means for protecting the high-voltage transistor, wherein the means includes a first adjustable resistor and a diode-connected transistor coupled in series between a common bus line and the gate terminal of the high-voltage transistor, and a second adjustable resistor coupled between the gate terminal of the high-voltage transistor and the supply voltage.