Semiconductor component and method for its production

• US 6,936,928 B2
• Filed: 09/23/2002
• Issued: 08/30/2005
• Est. Priority Date: 03/23/2000
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Hedler, Harry, Meyer, Thorsten
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US10/252,449
• Publication Number:
  US 20030057567A1
• Time in Patent Office: 1,072 Days
• Field of Search: 257/737, 257/738, 257/778, 438/108
• US Class Current: 257/778
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/13562 On the entire exposed surface of the core
• CPC Class Codes: H01L 2224/136 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12043 : Photo diode

Abstract

The invention proposes a semiconductor component with a semiconductor chip having a first main side with at least one contact pad thereon. A protective layer is applied on the first main side such that a clearance is provided around the contact pad. It is possible for the semiconductor component to be connected to a substrate using flip-chip bonding. Elevations that are connected to contact pads via conductor runs located on the protective layer are provided on the first main side. The elevations may be produced either by printable materials or by repeated electrodepositing of the ends of the conductor tracks lying opposite the contact pads.

Claims

1. A semiconductor component configured for connection to a standard substrate having contact points by using flip-chip bonding, the semiconductor component comprising:

a semiconductor chip having a first main side with at least two contact pads thereon;

a protective layer applied to said first side such that a clearance is configured around said two contact pads;

conductor runs located at least partially on said protective layer on said first main side;

a plurality of elevations each connected to a respective one of said contact pads by one of said conductor runs;

said plurality of said elevations having tips, said tips being bored into the contact points of the substrate to make an electrical contact, a distance between two of said plurality of said elevations corresponding to a distance between the contact points of the substrate; and

an adhesive developing a force between said semiconductor chip and the substrate for fixing a position of said elevations and the contact points after hardening.

2. The semiconductor component according to claim 1, wherein:

said plurality of said elevations taper in a direction away from said main side.

3. The semiconductor component according to claim 1, wherein:

said plurality of said elevations are made from a printable material;

each of said plurality of said elevations have an edge region and a vertex region; and

one of said conductor runs is directed along said edge region and ends on said vertex region of one of said plurality of said elevations.

4. The semiconductor component according to claim 1, wherein:

said plurality of said elevations are made from a material selected from a group consisting of a polymer and a polyimide.

5. The semiconductor component according to claim 1, wherein:

one of said conductor runs has an end formed by one of said plurality of said elevations;

said end of said one of said conductor runs lies opposite one of said two contact pads;

said end of said one of said conductor runs has a fissured surface that faces away from said first main side; and

said fissured surface is raised with respect to said conductor run and is created by at least one electrodepositing operation.

6. The semiconductor component according to claim 5, wherein:

said end of said one of said conductor runs is formed with a substantially annular shape.

7. The semiconductor component according to claim 6, wherein:

said end of said one of said conductor runs has a roughened edging; and

said edging is selected from a group consisting of an inner edging and an outer edging.

8. The semiconductor component according to claim 7, comprising:

a formation having a fissured surface;

said formation being applied on said end of said one of said conductor runs.

9. The semiconductor component according to claim 6, comprising:

a formation having a fissured surface;

said formation being applied on said end of said one of said conductor runs.

10. The semiconductor component according to claim 1, comprising:

a formation having a fissured surface;

one of said conductor runs having an end formed by one of said plurality of said elevations;

said end of said one of said conductor runs lying opposite one of said two contact pads; and

said formation being applied on said end of said one of said conductor runs.

11. The semiconductor component according to claim 10, wherein:

said formation is made from an electrically conductive material that can be electrodeposited.

12. The semiconductor component according to claim 1, wherein:

said conductor runs are conductor tracks including a copper-nickel-gold laminate.

13. A method for producing semiconductor components configured for connection to a standard substrate having contact points by using flip-chip bonding, the method which comprises:

providing each semiconductor component with a semiconductor chip having a first main side with at least two contact pads thereon;

applying a protective layer to the first side such that a clearance is configured around the two contact pads;

structuring the first main side of the semiconductor chips at a wafer level;

applying elevations on the first main side at the wafer level, the elevations having tips, the tips being bored into the contact points of the substrate to make an electrical contact, a distance between two of the elevations corresponding to a distance between the contact points of the substrate;

applying conductor runs to the first main side to connect the contact pads and the elevations;

performing the step of applying the conductor runs at a time selected from a group consisting of before performing the step of applying the elevations and after performing the step of applying the elevations;

applying an adhesive that develops a force between the semiconductor chips and the substrate for fixing a position of the elevations and the contact points after hardening; and

individually separating the semiconductor chips.

14. The method according to claim 13, wherein:

the elevations are printed on.

15. The method according to claim 13, which comprises:

electrodepositing ends of the conductor runs at least once;

the conductor runs being conductor tracks.

16. The method according to claim 13, which comprises:

applying a formation having a fissured surface to ends of the conductor runs before electrodepositing ends of the conductor runs;

the conductor runs being conductor tracks.