Method for testing an integrated circuit with an external potential applied to a signal output pin

• US 6,937,048 B2
• Filed: 12/11/2001
• Issued: 08/30/2005
• Est. Priority Date: 12/22/2000
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated), Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated), Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Inventors: Kurz, Alexander, Eichin, Matthias
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US10/021,746
• Publication Number:
  US 20020079916A1
• Time in Patent Office: 1,358 Days
• Field of Search: 324/765, 324/763, 324/158.1, 714/718, 714733-734, 714/726, 714/727
• US Class Current: 324/762.02
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

In previously known methods for testing internal signals of an integrated circuit, additional output pins were required which, in general, were linked to additional measuring pads within the integrated circuit.

In the new method, the circuit functions are tested by using the output pins at which the output signal is present during normal operation of the integrated circuit. By means of a simple, external connection, with which a defined voltage value is set at the signal output, the integrated circuit is switched by means of an integrated control unit into a test mode in which it applies selected signals, which are to be tested, at the signal output. There is no need for additional internal measuring pads or additional output pins.

Claims

1. A method of testing an integrated circuit comprising the steps:

a) providing at least one output signal generated by a circuit unit of said integrated circuit to at least one signal output pin of said integrated circuit during a normal operating mode;

b) externally applying an externally applied potential to at least one selected output pin among said at least one signal output pin;

c) evaluating a potential value of said externally applied potential;

d) dependent on and responsive to a result of said evaluating, switching from said normal operating mode into a test mode; and

e) during said test mode, generating in said circuit unit at least one test signal that is to be tested, and providing said at least one test signal to at least one chosen output pin among said at least one signal output pin.

2. The method according to claim 1, wherein said step b) comprises connecting a passive circuit component to said at least one selected output pin and generating said externally applied potential through said passive circuit component.

3. The method according to claim 2, wherein said step b) further comprises connecting said passive circuit component between said at least one selected output pin and a reference potential.

4. The method according to claim 2, wherein said passive circuit component comprises a resistor.

5. The method according to claim 1, wherein said at least one selected output pin in said step b) and said at least one chosen output pin in said step e) both comprise the same output pin among said at least one signal output pin.

6. The method according to claim 1, wherein said at least one signal output pin comprises plural signal output pins including a first output pin and a second output pin that is distinct and separate from said first output pin, said at least one selected output pin in said step b) is said first output pin, and said at least one chosen output pin in said step e) is said second output pin.

7. The method according to claim 1,

further comprising varying said externally applied potential so that said potential value of said externally applied potential is initially a first potential value and is then a second potential value different from said first potential value,

wherein said at least one test signal generated in said step e) comprises plural test signals including a first test signal and a second test signal different from said first test signal;

and

further comprising providing said first test signal to said chosen output pin dependent on and responsive to said evaluating in said step c) determining that said externally applied potential has said first potential value, and providing said second test signal to said chosen output pin dependent on and responsive to said evaluating in said step c) determining that said externally applied potential has said second potential value.

8. The method according to claim 7, wherein said circuit unit comprises plural circuit blocks including a first circuit block and a second circuit block, and further comprising activating said first circuit block and deactivating said second circuit block dependent on and responsive to said evaluating in said step c) determining that said externally applied potential has said first potential value, and activating said second circuit block and deactivating said first circuit block dependent on and responsive to said evaluating in said step c) determining that said externally applied potential has said second potential value.

9. The method according to claim 1, wherein said circuit unit comprises plural circuit blocks, and further comprising respectively activating and deactivating different ones of said circuit blocks dependent on and responsive to a result of said evaluating.

10. The method according to claim 1, wherein said steps d) and e) are carried out at a time separate from said steps b) and c), and not overlapping with said steps b) and c).

11. The method according to claim 1, wherein said evaluating in said step c) comprises comparing said potential value to at least one reference value.

12. The method according to claim 1, wherein said evaluating in said step c) comprises comparing said potential value to at least one reference value range defined by an upper reference value and a lower reference value, so as to determine whether said potential value falls in said reference value range.

13. The method according to claim 1, wherein said evaluating in said step c) comprises performing a logical operation on said potential value and a signal value of said at least one output signal generated by said circuit unit.

14. The method according to claim 13, wherein said step d) switches into said test mode only when said signal value is zero and said potential value lies in a prescribed potential value range.

15. The method according to claim 1, wherein said evaluating in said step c) comprises determining whether said potential value lies within a voltage interval of a voltage window discriminator, and said step d) switches into said test mode only when said potential value does lie within said voltage interval of said voltage window discriminator.

16. The method according to claim 15, wherein a signal value of said at least one test signal also lies within said voltage interval of said voltage window discriminator.