Integrated circuit that can be externally tested through a normal signal output pin

• US 6,937,051 B2
• Filed: 07/08/2004
• Issued: 08/30/2005
• Est. Priority Date: 12/22/2000
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated), Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Inventors: Kurz, Alexander, Eichin, Matthias
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US10/888,627
• Publication Number:
  US 20040239363A1
• Time in Patent Office: 418 Days
• Field of Search: 324/765, 324/763, 324/158.1, 714/718, 714733- 73
• US Class Current: 324/762.01
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

An integrated circuit can be tested externally at its normal signal output pin(s) without requiring additional testing output pins or test measuring pads. The integrated circuit includes a circuit unit that generates a normal output signal provided to the signal output pin in a normal operating mode and generates a test signal in a testing mode, a switching element that selectively does or does not connect the test signal from the circuit unit to the signal output pin, and a control unit that controls the switching element with a control signal responsive to the potential level present at the signal output pin. When the circuit is to be tested, a defined voltage is applied to the signal output pin by a voltage divider formed of resistors between a supply voltage and a reference voltage. This causes the control unit to close the switching element.

Claims

1. A circuit arrangement that can be externally tested through an output pin, comprising an integrated circuit that comprises:

a signal output pin;

a circuit unit having a test signal output;

a control unit having a testing input connected to said signal output pin for testing a potential at said signal output pin, and having a control output providing a control signal responsive to the testing of the potential; and

a switching element having a signal input connected to said test signal output of said circuit unit, a switched signal output connected to said signal output pin, and a control input connected to said control output of said control unit.

2. The circuit arrangement according to claim 1, further comprising:

an amplifier interposed between said test signal output of said circuit unit and said signal input of said switching element, for amplifying a test signal provided from said test signal output of said circuit unit to provide an amplified test signal via said amplifier and said switching element to said signal output pin; and

wherein said control unit comprises at least two comparators with inputs connected to said testing input of said control unit and forming a voltage window discriminator for comparatively testing the potential at said signal output pin; and

a logic gate having at least one input connected to and for performing a logic operation on outputs of said comparators and another output of said circuit unit, and having an output connected to said control output of said control unit, which is connected to said control input of said switching element and which is further connected to said circuit unit for selection of respective circuit elements within said circuit unit.

3. The circuit arrangement according to claim 1, further comprising at least one resistor connected to a reference voltage externally from said integrated circuit, and a switch arrangement interposed between said at least one resistor and said signal output pin of said integrated circuit for selectively connecting said signal output pin through a selected resistor among said at least one resistor to said reference voltage for establishing said potential at said signal output pin.

4. The circuit arrangement according to claim 3, wherein said integrated circuit further includes a load resistor connected between said signal output pin and a supply voltage.

5. The circuit arrangement according to claim 1, wherein:

said integrated circuit further includes a signal input pin; and

said circuit unit further includes a signal input connected to said signal input pin, and a normal signal output connected to said signal output pin.

6. The circuit arrangement according to claim 1, wherein said integrated circuit has only a single output pin being said signal output pin, and does not include any external test pin or measurement pad in addition to said signal output pin.

7. The circuit arrangement according to claim 1, wherein:

said signal output pin is a test signal output pin;

said integrated circuit further includes a normal signal output pin;

said integrated circuit further includes a signal input pin; and

said circuit unit further includes a signal input connected to said signal input pin, and a normal signal output connected to said normal signal output pin.

8. A circuit arrangement that can be externally tested through an output pin, comprising an integrated circuit that comprises:

a signal input pin;

a signal output pin;

a circuit unit having a signal input connected to said signal input pin, a normal signal output connected to said signal output pin, and a first test signal output;

a first switching element having a first signal input connected to said first test signal output, a first switched signal output that is connected to said signal output pin and selectively switched relative to said first signal input, and a first switch control input;

a control unit having a testing input connected to said signal output pin, and a first control output connected to said first switch control input, wherein said control unit is adapted to provide at said first control output a first control signal responsive to a potential level existing at said signal output pin; and

a load resistor connected between a supply voltage and said signal output pin.

9. The circuit arrangement according to claim 8, further comprising, external to said integrated circuit, a first test trigger switch and a first test trigger resistor connected in series between said signal output pin and a reference voltage different from said supply voltage.

10. The circuit arrangement according to claim 9, further comprising, external to said integrated circuit, a second test trigger switch and a second test trigger resistor connected in series between said signal output pin and said reference voltage and parallel to said first test trigger switch and said first test trigger resistor.

11. The circuit arrangement according to claim 8, wherein said control unit further has a normal signal checking input connected to said normal signal output, and said control unit is adapted to alter said first control signal responsive to a normal signal level present at said normal signal checking input.

12. The circuit arrangement according to claim 8, wherein said circuit unit includes signal processing circuitry adapted to process an input signal received via said signal input to produce a normal output signal at said normal signal output.

13. The circuit arrangement according to claim 12, wherein said circuit unit further has a circuit unit control input connected to said first control output of said control unit, and said circuit unit further includes test circuitry adapted to provide a test signal at said first test signal output responsive to said first control signal.

14. The circuit arrangement according to claim 8, wherein said control unit includes first and second comparators respectively having respective first and second comparator inputs connected via said testing input to said signal output pin and respectively having respective first and second comparator outputs, and an AND gate having a non-inverting gate input connected to said first comparator output, an inverting gate input connected to said second comparator output, and a gate output connected to said first control output.

15. The circuit arrangement according to claim 14, wherein said AND gate further has an inverting third input connected to said normal signal output.

16. The circuit arrangement according to claim 8, wherein:

said circuit unit further has a second test signal output;

said integrated circuit further comprises a second switching element having a second signal input connected to said second test signal output, a second switched signal output that is connected to said signal output pin and selectively switched relative to said second signal input, and a second switch control input; and

said control unit further has a second control output connected to said second switch control input, and said control unit is adapted to provide at said second control output a second control signal responsive to said potential level existing at said signal output pin.