Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics

• US 6,937,495 B2
• Filed: 09/24/2002
• Issued: 08/30/2005
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/253,075
• Publication Number:
  US 20030026120A1
• Time in Patent Office: 1,071 Days
• Field of Search: 365/75, 365/105, 365/189.01, 365/189.06, 365/189.07, 365/189.08, 365/189.09, 365/703, 365/706, 365/707, 365/214
• US Class Current: 365/105
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Claims

1. An integrated circuit comprising:

a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased;

a selection circuit for selecting one of a group of bit lines;

a bit line sensing circuit for determining the data state of a selected memory cell on the selected bit line, said sensing circuit comprising;

a bias isolation circuit for biasing the selected bit line coupled thereto at a selected bit line bias voltage and for conveying a current on the selected bit line onto a sense node while keeping the selected bit line substantially at the selected bit line bias voltage;

a reference current circuit for coupling to the sense node a reference current; and

a voltage amplifier circuit responsive to a voltage developed on the sense node by a net difference in current between the selected bit line current and the reference current.

2. The integrated circuit defined in claim 1 wherein:

the reference current has a magnitude between the first and second nominal current levels.

3. The integrated circuit defined in claim 1 wherein:

the memory array is a multi-level array having more than one memory plane.

4. The integrated circuit defined by claim 1 wherein the reference current circuit comprises:

a current mirror circuit having a first transistor and a second transistor whose respective control terminals are both coupled to a bias control node, for developing a voltage on the bias control node responsive to a current flowing thereinto, and for mirroring the current through the second transistor to form the reference current for the sense node coupled thereto.

5. The integrated circuit defined by claim 1 wherein the bias isolation circuit comprises:

a cascode transistor coupling a bit line input node of the bias isolation circuit to the sense node, said cascode transistor having a control terminal coupled to receive a cascode reference voltage.

6. The integrated circuit defined by claim 1 wherein the bias isolation circuit comprises:

a feedback amplifier circuit having an input terminal coupled to a bit line input node of the bias isolation circuit and an output terminal coupled to the sense node.

7. The integrated circuit defined by claim 5 wherein the bias isolation circuit further comprises:

a precharge circuit coupling the sense node to a suitable voltage node so that current flows through the cascode transistor in a direction to drive the selected bit line to a selected bit line bias voltage.

8. The integrated circuit defined by claim 7 wherein:

the suitable voltage node comprises a ground voltage node;

the cascode reference voltage has a nominal value equal to the selected bit line bias voltage less a threshold voltage of the cascode transistor; and

the precharge circuit discharges the selected bit line through the cascode transistor until the selected bit line reaches the selected bit line bias voltage.

9. The integrated circuit defined by claim 1 wherein:

the memory array also includes at least one noise detection line; and

the reference current coupled to the sense node is modulated by a noise current flowing through the noise detection line.

20. The integrated circuit defined in claim 1 further comprising:

a word line circuit for driving a selected word line from an unselected word line bias voltage to a selected word line bias voltage.

10. An integrated circuit comprising:

a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased;

a selection circuit for selecting one of a group of bit lines;

a bit line sensing circuit for determining the data state of a selected memory cell on the selected bit line, said sensing circuit comprising;

a bias isolation circuit for biasing the selected bit line coupled thereto at a selected bit line bias voltage and for conveying a current on the selected bit line onto a sense node while keeping the selected bit line substantially at the selected bit line bias voltage;

a reference current circuit for coupling to the sense node a reference current; and

a voltage amplifier circuit responsive to a voltage developed on the sense node by a net difference in current between the selected bit line current and the reference current;

wherein the reference current circuit comprises a current mirror circuit having a first transistor and a second transistor whose respective control terminals are both coupled to a bias control node, for developing a voltage on the bias control node responsive to a current flowing thereinto, and for mirroring the current through the second transistor to form the reference current for the sense node coupled thereto; and

wherein

the memory array also includes a noise detection line associated with a group of bit lines;

the selection circuit includes circuitry for selecting a noise detection line associated with the selected bit line; and

the reference current coupled to the sense node is modulated by a noise current flowing through the selected noise detection line.

11. The integrated circuit defined by claim 10 wherein the bias isolation circuit further comprises:

circuitry for biasing the selected noise detection line coupled thereto at the selected bit line bias voltage and for conveying a current on the selected noise detection line onto the bias control node while keeping the selected noise detection line substantially at the selected bit line bias voltage.

12. The integrated circuit defined by claim 11 further comprising:

a current source circuit connected directly to the bias control node.

13. The integrated circuit defined by claim 11 further comprising:

a current source circuit coupled to a noise detection line input node of the bit line sense circuit.

14. The integrated circuit defined by claim 11 wherein:

the voltage amplifier circuit includes a first input coupled to the sense node, and a second input coupled to a reference voltage.

15. The integrated circuit defined by claim 11 wherein:

the voltage amplifier circuit includes a first input coupled to the sense node, and a second input coupled to the bias control node.

16. The integrated circuit defined by claim 11 wherein the bias isolation circuit comprises:

a first cascode transistor coupling a bit line input node of the bias isolation circuit to the sense node; and

a second cascode transistor coupling a noise detection line input node of the bias isolation circuit to the bias control node;

wherein the first and second cascode transistors have a respective control terminal coupled to receive a cascode reference voltage.

17. The integrated circuit defined by claim 16 wherein the bias isolation circuit further comprises:

a first precharge circuit coupling the sense node to a suitable voltage node so that current flows through the first cascode transistor and drives the selected bit line to a selected bit line bias voltage;

a second precharge circuit coupling the sense node to the suitable voltage node so that current flows through the second cascode transistor and drives the selected noise detection line to the selected bit line bias voltage.

18. The integrated circuit defined by claim 17 wherein:

the suitable voltage node comprises a ground voltage node;

the cascode reference voltage has a nominal value equal to the selected bit line bias voltage less a threshold voltage of the cascode transistor;

the first precharge circuit discharges the selected bit line through the first cascode transistor until the selected bit line reaches the selected bit line bias voltage; and

the second precharge circuit discharges the selected noise detection line through the second cascode transistor until the selected noise detection line reaches the selected bit line bias voltage.

19. The integrated circuit defined by claim 11 wherein the bias isolation circuit further comprises:

a first precharge circuit coupling the bit line input node to a selected bit line bias voltage; and

a second precharge circuit coupling the noise detection line input node to the selected bit line bias voltage.

21. The integrated circuit defined by claim 11 wherein:

the memory array also includes a noise detection line associated with a group of bit lines;

the selection circuit includes circuitry for selecting a noise detection line associated with the selected bit line;

wherein the bias isolation circuit comprises a feedback amplifier circuit having a first input terminal coupled to a bit line input node, having a second input terminal coupled to a noise detection line input node, and having an output terminal coupled to the sense node.

22. The integrated circuit defined in claim 21 further comprising:

a first precharge circuit coupling the bit line input node to a selected bit line bias voltage; and

a second precharge circuit coupling the noise detection line input node to the selected bit line bias voltage.

23. An integrated circuit comprising:

a memory array having memory cells with an antifuse memory element and diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased;

a selection circuit for selecting one of a group of bit lines;

a bit line sensing circuit for determining the data state of a selected memory cell on the selected bit line, said sensing circuit comprising;

a bias isolation circuit for biasing the selected bit line coupled thereto at a selected bit line bias voltage and for conveying a current on the selected bit line onto a sense node while keeping the selected bit line substantially at the selected bit line bias voltage;

a reference current circuit fur coupling to the sense node a reference current; and

a voltage amplifier circuit responsive to a voltage developed on the sense node by a net difference in current between the selected bit line current and the reference current.

24. The integrated circuit defined in claim 23 wherein:

the reference current has a magnitude between the first and second nominal current levels.

25. The integrated circuit defined an claim 23 wherein:

the memory array is a multi-level array having more than one memory plane.

26. The integrated circuit defined by claim 23 wherein the reference current circuit comprises:

a current mirror circuit having a first transistor and a second transistor whose respective control terminals are both coupled to a bias control node, for developing a voltage on the bias control node responsive to a current flowing thereinto, and for mirroring the current through the second transistor to form the reference current for the sense node coupled thereto.

27. The integrated circuit defined by claim 26 further comprising:

a current source circuit connected directly to the bias control node of the current mirror circuit.

28. The integrated circuit defined by claim 23 wherein the bias isolation circuit comprises:

a cascode transistor coupling a bit line input node of the bias isolation circuit to the sense node, said cascode transistor having a control terminal coupled to receive a cascode reference voltage.

29. The integrated circuit defined by claim 23 wherein the bias isolation circuit comprises:

a feedback amplifier circuit having an input terminal coupled to a bit line input node of the bias isolation circuit and an output terminal coupled to the sense node.

30. The integrated circuit defined by claim 29 wherein the feedback amplifier circuit comprises:

an amplifier circuit incorporating resistive feedback between the sense node and the bit line input node.

31. The integrated circuit defined by claim 28 wherein the bias isolation circuit further comprises:

a precharge circuit coupling the sense node to a suitable voltage node so that current flows through the cascode transistor in a direction to drive the selected bit line to a selected bit line bias voltage.

32. The integrated circuit defined by claim 31 wherein:

the suitable voltage node comprises a ground voltage node;

the cascode reference voltage has a nominal value equal to the selected bit line bias voltage less a threshold voltage of the cascode transistor; and

the precharge circuit discharges the selected bit line through the cascode transistor until the selected bit line reaches the selected bit line bias voltage.

33. The integrated circuit defined by claim 28 wherein the bias isolation circuit further comprises:

a precharge circuit coupling the bit line input node to a selected bit line bias voltage.

34. The integrated circuit defined by claim 33 wherein:

the precharge circuit comprises an amplifier circuit incorporating active feedback.

35. The integrated circuit defined by claim 33 wherein:

the precharge circuit comprises a transfer gate-style circuit.

36. The integrated circuit defined by claim 35 wherein:

the precharge circuit comprises a single transistor.

37. The integrated circuit defined by claim 23 wherein:

the memory array also includes at least one noise detection line; and

the reference current coupled to the sense node is modulated by a noise current flowing through the noise detection line.

51. The integrated circuit defined in claim 23 further comprising:

a word line circuit for driving a selected word line from an unselected word line bias voltage to a selected word line bias voltage.

38. An integrated circuit comprising:

a memory array having memory cells with an antifuse memory element and diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased;

selection circuit for selecting one of a noun of bit lines;

a bit line sensing circuit for determining the data state of a selected memory cell on the selected bit line, said sensing circuit comprising;

a bias isolation circuit for biasing the selected bit line coupled thereto at a selected bit line bias voltage and for conveying a current on the selected bit line onto a sense node while keeping the selected bit line substantially at the selected bit line bias voltage;

a reference current circuit for coupling to the sense node a reference current; and

a voltage amplifier circuit responsive to a voltage developed on the sense node by a net difference in current between the selected bit line current and the reference current;

wherein the reference current circuit comprises a current mirror circuit having a first transistor and a second transistor whose respective control terminals are both coupled to a bias control node, for developing a voltage on the bias control node responsive to a current flowing thereinto, and for mirroring the current through the second transistor to form the reference current for the sense node coupled thereto; and

wherein

the memory array also includes a noise detection line associated with a group of bit lines;

the selection circuit includes circuitry for selecting a noise detection line associated with the selected bit line; and

the reference current coupled to the sense node is modulated by a noise current flowing through the selected noise detection line.

39. The integrated circuit defined by claim 38 wherein the bias isolation circuit further comprises:

circuitry for biasing the selected noise detection line coupled thereto at the selected bit line bias voltage and for conveying a current on the selected noise detection line onto the bias control node while keeping the selected noise detection line substantially at the selected bit line bias voltage.

40. The integrated circuit defined by claim 39 further comprising:

a current source circuit connected directly to the bias control node.

41. The integrated circuit defined by claim 39 further comprising:

a current source circuit coupled to a noise detection line input node of the bit line sense circuit.

42. The integrated circuit defined by claim 39 wherein:

the voltage amplifier circuit includes a first input coupled to the sense node, and a second

input coupled to a reference voltage.

43. The integrated circuit defined by claim 39 wherein:

the voltage amplifier circuit includes a first input coupled to the sense node, and a second input coupled to the bias control node.

44. The integrated circuit defined by claim 39 wherein the bias isolation circuit comprises:

a first cascode transistor coupling a bit line input node of the bias isolation circuit to the sense node; and

a second cascode transistor coupling a noise detection line input node of the bias isolation circuit to the bias control node;

wherein the first and second cascode transistors have a respective control terminal coupled to receive a cascode reference voltage.

45. The integrated circuit defined by claim 44 wherein the bias isolation circuit further comprises:

a first precharge circuit coupling the sense node to a suitable voltage node so that current flows through the first cascode transistor and drives the selected bit line to a selected bit line bias voltage;

a second precharge circuit coupling the sense node to the suitable voltage node so that current flows through the second cascode transistor and drives the selected noise detection line to the selected bit line bias voltage.

46. The integrated circuit defined by claim 45 wherein:

the suitable voltage node comprises a ground voltage node;

the cascode reference voltage has a nominal value equal to the selected bit line bias voltage less a threshold voltage of the cascode transistor;

the first precharge circuit discharges the selected bit line through the first cascode transistor until the selected bit line reaches the selected bit line bias voltage; and

the second precharge circuit discharges the selected noise detection line through the second cascode transistor until the selected noise detection line reaches the selected bit line bias voltage.

47. The integrated circuit defined by claim 39 wherein the bias isolation circuit further comprises:

a first precharge circuit coupling the bit line input node to a selected bit line bias voltage; and

a second precharge circuit coupling the noise detection line input node to the selected bit line bias voltage.

48. The integrated circuit defined by claim 47 wherein:

the first and second precharge circuits each comprises an amplifier circuit incorporating active feedback.

49. The integrated circuit defined by claim 47 wherein:

the first and second precharge circuits each comprises a transfer gate-style circuit.

50. The integrated circuit defined by claim 49 wherein:

the first and second precharge circuits each comprises a single transistor.

52. The integrated circuit defined by claim 39 wherein:

the memory array also includes a noise detection line associated with a group of bit lines;

the selection circuit includes circuitry for selecting a noise detection line associated with the selected bit line;

wherein the bias isolation circuit comprises a feedback amplifier circuit having a first input terminal coupled to a bit line input node, having a second input terminal coupled to a noise detection line input node, and having an output terminal coupled to the sense node.

53. The integrated circuit defined by claim 52 wherein the feedback amplifier circuit comprises:

an active amplifier circuit incorporating resistive feedback between one of its input nodes and its output node.

54. The integrated circuit defined in claim 52 further comprising:

a first precharge circuit coupling the bit line input node to a selected bit line bias voltage; and

a second precharge circuit coupling the noise detection line input node to the selected bit line bias voltage.

55. The integrated circuit defined by claim 54 wherein:

the first and second precharge circuits each comprises an amplifier circuit incorporating active feedback.

56. The integrated circuit defined by claim 54 wherein:

the first and second precharge circuits each comprises a transfer gate-style circuit.

57. The integrated circuit defined by claim 56 wherein:

the first and second precharge circuits each comprises a single transistor.

58. The integrated circuit defined in claim 52 wherein:

the voltage amplifier circuit comprises a single-ended amplifier circuit.

59. The integrated circuit defined in claim 52 wherein:

the voltage amplifier circuit comprises a differential amplifier circuit having a first input terminal coupled to the sense node, and having a second input terminal coupled to a reference voltage.