Programming and erasing methods for a non-volatile memory cell

• US 6,937,521 B2
• Filed: 05/28/2002
• Issued: 08/30/2005
• Est. Priority Date: 05/04/2000
• Status: Expired due to Term

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Avni, Dror
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US10/155,216
• Publication Number:
  US 20030002345A1
• Time in Patent Office: 1,190 Days
• Field of Search: 365/185.22, 365/185.19, 365/185.29
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

Claims

1. A method for erasing a memory array comprising:

adapting a parameter of an erase pulse as a function of the difference between the current threshold voltage of a cell of said memory array and an erase threshold value; and

applying the erase pulse to a terminal of a cell of said array selected from the group consisting of gate, drain and source.

2. A method according to claim 1 wherein said step of adapting includes the steps of:

determining erase conditions of the erase pulse used to erase a representative portion of said memory array; and

setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said representative portion.

3. A method according to claim 1 and wherein said step of adapting includes the steps of:

measuring the current threshold level of a bit to within a predetermined range; and

selecting either an incremental voltage level or an incremental duration of a next erase pulse for said bit in accordance with said measured current threshold level.

4. A method according to claim 3 and wherein said step of measuring includes the step of having multiple verify levels for said array.

5. A method according to claim 3 and wherein said step of measuring also includes the step of after an erase pulse, comparing a threshold level of a group of bits which have received said erase pulse to at least one of said verify levels and said step of selecting includes the step of selecting a next erase pulse level according to either the lowest or the highest verify level achieved by said group.

6. A method according to claim 5 and also comprising the steps of removing a bit which has been erased from said group and repeating said steps of comparing and selecting until there are no more bits in said group.

7. A method according to claim 3 and wherein said step of measuring also includes the step of after an erase pulse, comparing a threshold level of a bit which received said erase pulse to at least one of said verify levels and said step of setting includes the step of selecting a next erase pulse level according to either the lowest or the highest verify level achieved by said bit.

8. A method according to claim 2 and wherein said erase conditions comprises at least one of the following set:

a gate voltage level, a drain voltage level, an erase pulse duration, a pulse high voltage level, a pulse low voltage level, a pulse rise ramp rate, a pulse fall ramp rate, the terminal to which the pulse is applied, and any combination thereof.