Method of compensating frequency error in communication system and apparatus for the same

• US 6,937,673 B2
• Filed: 12/30/2002
• Issued: 08/30/2005
• Est. Priority Date: 12/29/2001
• Status: Expired due to Fees

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kim, Jong Heon
• Primary Examiner(s): Corrielus, Jean B.
• Application Number:
  US10/330,334
• Publication Number:
  US 20030123527A1
• Time in Patent Office: 974 Days
• Field of Search: 375/130, 375/140, 375/144, 375/147, 375/148, 375/344, 375/346, 375/348, 375/285, 375/372, 375/362, 370/525, 370/491, 455/71, 455/192.1, 455/192.2, 455/205
• US Class Current: 375/344
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04L 2027/0046 Open loops

Abstract

Disclosed is a method of compensating a frequency error and an apparatus for the same in the communication system suitable to the frequency error compensation. The method includes the steps of despreading the signal, estimating a frequency error value by differentiating the despread signal, generating a tone based on the frequency error value, and compensating for a frequency error of the despread signal based on the tone.

Claims

1. A method of compensating a frequency error in a communication system, comprising:

estimating a frequency error value by differentiating a pilot signal of a received signal;

generating an address signal corresponding to the frequency error value;

generating a tone from at least one memory based on the address signal; and

compensating a data signal of the received signal for frequency error based on the tone.

2. The method of claim 1, wherein compensating the data signal of the received signal for frequency error compensates at a symbol level.

3. The method of claim 1, further comprising:

latching the tone mapped to the address signal corresponding to symbols-length of the data signal.

4. The method of claim 3, wherein generating said address signal generates the address signal for a positive tone sample if a polarity of the frequency error value is negative.

5. The method of claim 3, wherein generating said address signal generates the address signal for a negative tone sample if a polarity of the frequency error value is positive.

6. The method of claim 3, wherein generating said address signal generates the address signal for a tone sample having a frequency increased in proportion to the frequency error value.

7. The method of claim 3, further comprising outputting first tone samples mapped onto a first address signal and second tone samples, which are mapped onto a second address signal having a predetermined frequency offset over the first tone samples.

8. The method of claim 3, wherein said address signal is adjusted so as not to get out of a size of corresponding storing section which store the tone sample.

9. The method of claim 1, wherein compensating the data signal of the received signal for frequency error compensates at a chip level.

10. A method comprising:

despreading a received signal;

estimating a frequency error value by differentiating the despread signal;

generating a tone based on the frequency error value;

generating addresses corresponding to the frequency error value and a control signal according to a type of the addresses;

latching tone samples mapped onto the addresses corresponding to a length of chips of the despread signal; and

compensating the despread signal for frequency error based on the tone.

11. The method of claim 10, wherein generating generates the addresses for positive tone samples if a polarity of the frequency error value is negative.

12. The method of claim 10, wherein generating generates the addresses for negative tone samples if a polarity of the frequency error value is positive.

13. The method of claim 10, wherein generating generates the addresses for tone samples having a frequency increased in proportion to the frequency error value.

14. The method of claim 10, further comprising:

outputting with a time division method first tone samples mapped onto a first address and second tone samples, which are mapped onto a second address and have a predetermined phase offset over the first tone samples; and

demultiplexing the first tone samples and the second tone samples according to the control signal.

15. The method of claim 10, wherein the addresses are adjusted so as not to get out of a size of a storing section which stores the tone samples.

16. The method of claim 14, wherein the first address and the second address are outputted according to the time division method.

17. The method of claim 10, further comprising:

outputting complex tone samples of first tone samples mapped onto a first address and second tone samples, which are mapped onto a second address and have a predetermined phase offset over the first tone samples; and

demultiplexing the first tone samples and the second tone samples according to the control signal.

18. An apparatus for correcting frequency error in a communication system, comprising:

differentiating means for differentiating a pilot signal of a received signal to estimate a frequency error value;

a tone generator for generating a tone based on an address signal, wherein the tone generator comprises;

an address generator for generating the address signal based on the frequency error value, and

at least one memory for storing tone samples to output the tone corresponding to the address signal; and

a compensator for compensating a data signal of the received signal for frequency error based on the tone.

19. The apparatus of claim 18, wherein the compensator compensates the data signal of the received signal for frequency error at a symbol level.

20. The apparatus of claim 18, further comprising:

a plurality of latch means for latching the output of the at least one memory corresponding to a symbol rate of the data signal.

21. The apparatus of claim 20, wherein the address generator generates the address signal for positive tone samples if a polarity of the frequency error value is negative.

22. The apparatus of claim 20 wherein the address generator generates the address signal for negative tone samples if a polarity of the frequency error value is positive.

23. The apparatus of claim 20, wherein the address generator generates the address signal for tone samples having a frequency increased in proportion to the frequency error value.

24. The apparatus of claim 20, wherein the at least one memory comprises a plurality of memories for generating first tone samples mapped Onto a first address signal and second tone samples, which are mapped onto a second address signal and have a predetermined frequency offset over the first tone samples.

25. The apparatus of claim 24, wherein the address generator adjusts the first and second address signals so as not to exceed a size of the memories.

26. The apparatus of claim 18, wherein the compensator compensates the data signal of the received signal for frequency error at a chip level.

27. An apparatus for correcting a frequency error in a communication system comprising:

differentiating means for differentiating a pilot signal of a received signal to estimate a frequency error value;

a tone generator for generating a tone based on an address signal, wherein the tone generator comprises;

an address generator for generating the address signal based on the frequency error value, and

at least one memory for storing tone samples to output the tone corresponding to the address signal; and

a compensator for compensating the received signal for frequency error based on the tone.

28. The apparatus of claim 27, wherein the address generator generates the address signal for positive tone samples if a polarity of the frequency error value is negative.

29. The apparatus of claim 27, wherein the address generator generates the address signal for negative tone samples if a polarity of the frequency error value is positive.

30. The apparatus of claim 27, wherein the address generator generates the address signal for tone samples having a frequency increased in proportion to the frequency error value.

31. The apparatus of claim 27, wherein the at least one memory comprises a memory for storing first tone samples mapped onto a first address signal and second tone samples, which are mapped onto a second address signal and have a predetermined phase offset over the first tone samples and outputting the tone samples with a time division method;

and

a demultiplexer for demultiplexing the first tone samples and the second tone samples according to a control signal.

32. The apparatus of claim 31, wherein the address generator adjusts the first and second address signals so as not to exceed a size of the memory.

33. The apparatus of claim 31, wherein the address generator outputs the first address signal and the second address signal according to the time division method.

34. The apparatus of claim 27, wherein the at least one memory comprises a memory for outputting complex tone samples of first tone samples mapped onto a first address signal and second tone samples, which are mapped onto a second address signal and have a predetermined phase offset over the first tone samples and storing the tone samples;

and

demultiplexing the first tone samples and the second tone samples according to a control signal.

35. The apparatus of claim 27, wherein the tone generator further comprises a plurality of latch means for latching the output of the memory corresponding to a pseudo noise (PN) chip rate.

36. The apparatus of claim 27, wherein the received signal comprises an output signal having a multiplied pseudo noise (PN) code.