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Circuit and method for implementing the advanced encryption standard block cipher algorithm in a system having a plurality of channels

  • US 6,937,727 B2
  • Filed: 06/08/2001
  • Issued: 08/30/2005
  • Est. Priority Date: 06/08/2001
  • Status: Expired due to Fees
First Claim
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1. A circuit for implementing the Advanced Encryption Standard (AES) block cipher algorithm in a system having a plurality of channels, the circuit comprising:

  • round key generation means for (i) selectively receiving a cipher key and (ii) generating a round key of a first predetermined bit length from the received cipher key a predetermined number of times based on the AES Rijndael key expansion algorithm;

    encryption/decryption means for (i) selectively receiving a data block of the first predetermined bit length from one of the plurality of system channels and a round key from the round key generation means and (ii) encrypting/decrypting the received data block a predetermined number of rounds based on the AES block cipher algorithm; and

    controller means, responsive to control signals from each of the plurality of system channels, for controlling the round key generation means and the encryption/decryption means to selectively encrypt or decrypt the data block from individual ones of the plurality of system channels in a round-robin fashion.

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