Data processing apparatus and data processing method

• US 6,938,078 B1
• Filed: 11/15/1999
• Issued: 08/30/2005
• Est. Priority Date: 12/09/1998
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yamada, Yoshihisa
• Primary Examiner(s): Coulter, Kenneth R.
• Application Number:
  US09/440,157
• Time in Patent Office: 2,115 Days
• Field of Search: 709/213, 709/214, 709/215, 709/216, 709/220, 709/221, 712/13, 712/14, 712/15
• US Class Current: 709/220
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A data processing apparatus of the present invention includes a plurality of nodes each of which includes at least one processor and which is divided to a plurality groups, a bus to which the nodes are connected, and memory elements provided in the nodes, respectively. Shared memory areas are provided in the groups, respectively, and the nodes access to the shared memory areas. Another data processing apparatus of the present invention includes a plurality of nodes each of which includes at least one processor, a bus to which the nodes are connected, and memory elements provided in the nodes, respectively. The apparatus has a first element which sets the nodes to clusters. A method for data processing in a data processing apparatus, which includes a plurality of nodes divided to a plurality of groups, a bus to which the nodes are connected, and shared memory areas corresponding to the groups, respectively, includes outputting a request addressed to the shared memory area to the bus by one of the node, determining in each of the nodes whether the shared memory, to which the request is addressed, is owned by its one node, and accessing to the shared memory in one of the nodes which determines the shared memory is owned by its own node during the determining step.

Claims

1. A data processing apparatus comprising:

a plurality of nodes each of which includes at least one processor;

a bus to which said nodes are connected;

memory elements provided in said nodes, respectively;

a first element which sets said nodes to clusters; and

shared memory areas which are provided in said clusters, respectively, and to which said nodes of any of said clusters access;

wherein said first element includes a first register which indicates said clusters to which said nodes belong and a second register which indicates whether or not said apparatus operates in said clusters.

2. The data processing apparatus as claimed in claim 1,

wherein said first element includes a third register which indicates which of said node has said shared memory area.

3. The data processing apparatus as claimed in claim 2, wherein said first element determines whether the access is addressed to said shared memory area of its own cluster or the other clusters.

4. The data processing apparatus as claimed in claim 1, wherein said first element detects an illegal access which is addressed beyond a predetermined address range.

5. The data processing apparatus as claimed in claim 4, wherein said first element includes a third register which indicates said predetermined address range.

6. The data processing apparatus as claimed in claim 1, further comprising a specific memory area which corresponds to each of said clusters and in which an access from the other clusters is inhibited.

7. The data processing apparatus as claimed in claim 6, wherein said first element determines whether the access is addressed to said specific memory area of its own cluster or the other clusters.

8. The data processing apparatus as claimed in claim 1, wherein a plurality of said nodes belongs to one cluster.

9. A data processing apparatus comprising:

a plurality of nodes each of which includes at least one processor, each node belonging to a group among a plurality groups;

a bus to which said nodes are connected;

memory elements provided in said nodes, respectively;

shared memory areas which are provided in said groups, respectively, and to which said nodes of any of said groups access; and

first elements which are provided in said nodes, respectively, and which identify groups to which the nodes belong;

wherein said first element includes a first register to indicate the groups to which said nodes belong and a second register which indicates whether or not said apparatus operates in said groups.

10. The data processing apparatus as claimed in claim 9, wherein said nodes communicate with each other by using said shared memory.

11. The data processing apparatus as claimed in claim 9, wherein each of said groups are operated by a corresponding operating system.

12. The data processing apparatus as claimed in claim 9, further comprising a specific memory area which corresponds to each of said groups and in which an access from the other groups is inhibited.

13. The data processing apparatus as claimed in claim 9, wherein a plurality of said nodes belongs to one group.