Processor with multiple-thread, vertically-threaded pipeline

• US 6,938,147 B1
• Filed: 05/11/1999
• Issued: 08/30/2005
• Est. Priority Date: 05/11/1999
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Chamdani, Joseph I., Tremblay, Marc, Lauterbach, Gary, Joy, William N.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US09/309,732
• Time in Patent Office: 2,303 Days
• Field of Search: 712/23, 712/28, 712/239, 711/117
• US Class Current: 712/28
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Claims

1. A processor comprising:

a shared processor pipeline that includes therein a plurality of multiple-bit flip-flops, each multiple-bit flip-flop capable of concurrently holding in the shared processor pipeline, at least a portion of thread state for a plurality of execution treads, one of the execution threads being actively executed in the shared processor pipeline at a given time; and

thread control logic coupled to the shared processor pipeline and cap able of controlling the shared processor pipeline to select thread state for an active one of the execution threads, including the portion of the thread state represented in the multiple-bit flip-flops of the shared processor pipeline.

2. A processor according to claim 1 wherein the plurality of multiple-bit flip-flops are capable of generating multiple thread paths without using multiplexers to select from among the plurality of execution threads.

3. A processor according to claim 1 wherein the plurality of multiple-bit flip-flops are fabricated in circuits the size of single-bit flip-flops so that multiple threads are supported without increasing the surface area of the integrated circuit, maintaining the footprint of single-thread circuits so that integrated circuit die size is maintained.

4. A processor according to claim 1, wherein the multile-bit flip-flops include a plurality of latches controlled by thread switches.

5. A processor according to claim 4 wherein the latches are removed from a direct path of signal propagation so that signal speed is not degraded.

6. A processor according to claim 1 further comprising:

a register file coupled to the shared processor pipeline and capable of supplying data to the processor pipeline for execution.

7. A processor according to claim 1 further comprising:

a register file coupled to the shared processor pipeline and capable of supplying data to the processor pipeline for execution, the register file being a multiple-dimensional register file that includes a plurality of two-dimensional storage planes.

8. A processor comprising:

a shared processor pipeline including a plurality of pulse-based multiple-bit high-speed flip-flops, each pulse-based multiple-bit high-speed flip-flop including a plurality of latches, wherein the shared processor pipeline includes a plurality of processing units capable of executing a plurality of instructions in parallel, the shared processor pipeline being capable of concurrently holding a plurality of execution threads, one of the plurality of execution threads being actively executed; and

a thread control logic coupled to the shared processor pipeline that is capable of controlling the shared processor pipeline to select a thread machine state of the plurality of execution threads to be in either an actively executed state or a held state.

9. A processor according to claim 8 further comprising:

the plurality of processing units including one or more integer arithmetic logic units and one or more floating point arithmetic logic units.

10. A processor according to claim 8 further comprising:

the plurality of processing units including one or more graphic units.

11. A processor according to claim 8 wherein an individual processing unit of the plurality of processing units further includes:

a plurality of load/store units coupled to the shad processor pipeline, the plurality of load/store units being respectively allocated to the plurality of execution threads.

12. A processor according to claim 8 further comprising:

a plurality of load/store units coupled to the shared processor pipeline, the plurality of load/store units being respectively allocated to the plurality of execution threads; and

an external cache control unit coupled to the plurality of load/store units, the load/store units being shared among the plurality of execution threads and being shared among the plurality of processing units.

13. A processor according to claim 8 wherein an individual processing unit of the plurality of processing units further includes:

a data storage unit coupled to the execution pipeline and shared among the plurality of execution threads.

14. A processor according to claim 13 wherein the data storage unit further includes:

a data cache coupled to the execution pipeline and shared among the plurality of execution threads; and

a data memory management unit coupled to the data cache.

15. A processor according to claim 8 wherein an individual processing unit of the plurality of processing units further includes:

an instruction control logic coupled to the shared processor pipeline and shared among the plurality of execution threads.

16. A processor according to claim 15 wherein the instruction control logic further includes:

an instruction cache coupled to the shared processor pipeline;

a branch predict logic coupled to the instruction cache; and

an instruction memory management unit coupled to the instruction cache and coupled to the branch predict logic.

17. A processor according to claim 8, further comprising:

a tag RAM integrated into the single integrated circuit, the tag RAM supporting a two-way external cache, the tag RAM being shared among the plurality of processing units.

18. A processor comprising:

a plurality of processing units that operate in a shared processor pipeline, the shrub processor pipeline including a plurality of pulse-based multiple-bit high-ed flip-flops, each pulse-based multiple-bit high-speed flip-flop including a plurality of latches, wherein the plurality of processing units are capable of concurrently holding a plurality of execution threads as a plurality of shadow states, the individual shadow states being respectively allocated to an execution thread of a plurality of execution threads; and

a thread control logic coupled to the shared processor pipeline that is capable of controlling the shared processor pipeline to select a thread machine state of the plurality of execution threads, the thread machine state of the individual execution threads being an actively executed state or a held state.

19. A processor according to claim 18 further comprising:

an external cache control unit coupled to the plurality of processing units and shared among the plurality of execution threads, the external cache control unit being coupled to an external cache RAM.

20. A processor according to claim 18 further comprising:

a memory control unit coupled to the external cache control unit, the memory control unit including a cache miss processing and interfacing logic for supplying a plurality of execution threads to the plurality of processing units in thread processing.

21. A processor according to claim 18 further comprising:

a Peripheral Component Interconnect (PCI) interface coupled to the external cache control unit.

22. A processor according to claim 18 wherein the processor is integrated into a single integrated circuit.

23. A processor comprising:

a plurality of processing units in a single integrated circuit that are each capable of executing respective pluralities of execution threads in respective pipelines thereof, the pipelines each being capable of concurrently representing therein at least a portion of thread state for plural execution threads, the pipelines including a plurality of multiple-bit flip-flops, each multiple-bit flip-flop including a plurality of latches for representing respective ones of the thread states;

thread control logic coupled to at least one of the pipelines and capable of controlling the pipeline to select an active one of the represented thread states; and

an external cache control unit coupled to the pipelines and shared thereamongst.

24. A processor according to claim 23 further comprising:

an external cache arbiter integrated into the single integrated circuit and coupled to the external cache control units of the plurality of processing units.

25. A processor according to claim 23 further comprising:

an external cache arbiter integrated into the single integrated circuit and coupled to the external cache control units of the plurality of processing units; and

a cache integrated into the single integrated circuit and coupled to the external cache arbiter.

26. A processor according to claim 23 wherein the multiple-bit flip-flops have a latch structure coupled to a plurality of select-bus lines, the select-bus lines selecting an active thread from among the plurality of execution threads.

27. A processor according to claim 23 wherein an individual processing unit of the plurality of processing units further includes:

a memory control unit coupled to the external cache control unit.

29. A processor according to claim 23, further comprising:

a multiple-dimension register file coupled to the pipelines, the multiple-dimension register file including register instances replicated for storage of register state for respective execution threads concurrently represented in the pipelines.

30. A processor according to claim 23, wherein the multiple-bit flip-flops arm pulse-based.

28. A processor according to 23 wherein an individual processing unit of the plurality of processing units further includes:

a Peripheral Component Interconnect (PC) interface coupled to the external cache control unit.

31. A method of operating a processor comprising:

concurrently representing thread states for a plurality of execution threads in multiple-bit flip-flops of a shed processor pipeline each multiple-bit flip-flop including a plurality of latches for representing a portion of the respective thread states;

actively executing one of the plurality of execution threads; and

controlling the shared processor pipeline to select a respective one of the concurrently represented thread states.

32. A method according to claim 31, further comprising:

representing, using replicated register instances, register state for respective execution threads for which thread state is concurrently represented in the shared processor pipeline.

33. A processor comprising:

a shared processor pipeline including a plurality of pulse-based multiple-bit flip-flops, each pulse-based multiple-bit flip-flop including a plurality of latches, wherein the shared processor pipeline is capable of concurrently representing at least a portion of thread state for a plurality of execution threads, one of the plurality of execution threads being actively executed, at least a portion of thread state for others of the plurality of execution threads being held within the shared processor pipeline pending selection for execution; and

thread control logic coupled to the shared processor pipeline that is capable of controlling activation and deactivation of the plurality of execution threads in the shared processor pipeline.

34. A processor according to claim 33, further comprising:

a multiple-dimension register file coupled to the shared processor pipeline, the multiple-dimension register file including register instances replicated for storage of register state for respective execution threads concurrently represented in the shared processor pipeline.

35. A processor comprising:

a vertically multithreaded processor pipeline including a plurality of pipeline registers defined therein that include, for respective storage positions thereof, multiple-bit flip-flops wherein respective ones of the multiple-bits encode at least a portion of thread state for respective execution threads concurrently represented in the processor pipeline; and

thread control logic coupled to the processor pipeline and selective for the respective bits of the multiple-bit flip-flops, which correspond to an active one of the execution threads.

36. A processor according to claim 35, further comprising:

a multiple-dimension register file coupled to the processor pipeline, the multiple-dimension register file including register instances replicated for storage of register state for respective execution threads concurrently represented in the processor pipeline.

37. A processor according to claim 35, wherein the multiple-bit flip-flops are pulse-based.