Method and system for allowing code to be securely initialized in a computer

• US 6,938,164 B1
• Filed: 11/22/2000
• Issued: 08/30/2005
• Est. Priority Date: 11/22/2000
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: England, Paul, Willman, Bryan
• Primary Examiner(s): Rimell, Sam
• Assistant Examiner(s): Betit, Jacob F.
• Application Number:
  US09/721,398
• Time in Patent Office: 1,742 Days
• Field of Search: 713/200, 713/189, 713/190, 713/1, 713/187, 713/188, 713/2, 713/164, 713/193, 713/194, 713/192, 713/100, 380/259
• US Class Current: 713/193
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).

Claims

1. An apparatus comprising:

a processor reset portion to assert a reset signal to a processor;

a memory protector portion to prevent any bus master from accessing memory until the processor completes execution of a trusted core initialization process; and

a controller, coupled to the memory protector portion, to;

map a processor reset vector to an initialization vector;

receive a read request corresponding to the processor reset vector from the processor;

return, in response to the read request, the initialization vector to the processor; and

allow the processor to access the memory beginning with the initialization vector.

2. An apparatus as recited in claim 1, wherein the controller is further to:

re-map the processor reset vector to an additional processor start vector after returning the initialization vector to the processor; and

return, in response to another read request corresponding to the processor reset vector from another processor, the additional processor start vector.

47. One or more computer-readable media as recited in claim 1, wherein the plurality of instructions further cause the one or more processors to perform acts including loading microcode from the trusted core in memory into the one central processing unit after resetting the central processing unit.

48. One or more computer-readable media as recited in claim 1, wherein the resetting comprises asserting, on a processor bus, a RESET# signal to each of the one or more central processing units.

3. A memory controller comprising:

a first interface to allow communication with a processor;

a second interface to allow communication with a system memory; and

a controller, coupled to the first interface and the second interface, to reset a processor and to allow the processor to execute a code initialization process while preventing any other processors from accessing the system memory;

wherein the controller is further to;

map a processor reset vector to an initialization vector;

receive a read request corresponding to the processor reset vector from the processor;

return, in response to the read request, the initialization vector to the processor; and

allow the processor to access the memory beginning with the initialization vector.

4. A memory controller as recited in claim 3, wherein the memory controller is included in a processor.

5. A memory controller as recited in claim 3, wherein the first interface comprises a processor bus interface.

6. A memory controller as recited in claim 5, wherein the memory controller operates without requiring the processor bus interface to support any additional commands on the processor bus.

7. A memory controller as recited in claim 3, wherein the system memory comprises a dynamic random access memory.

8. A memory controller as recited in claim 3, wherein the controller is further to allow the processor to execute the code initialization process while preventing any bus masters from accessing the system memory.

9. A memory controller as recited in claim 3, wherein the controller is further to:

reset any other processor coupled to the memory controller prior to allowing the processor to execute the code initialization process;

prevent any other processor and any bus master coupled to the memory controller from accessing the system memory until the processor executes the code initialization process; and

after execution of the code initialization process, allow any other central processing units coupled to the memory controller and any bus masters coupled to the memory controller to access the memory.

10. A memory controller as recited in claim 3, wherein the initialization vector is an address within the code initialization process.

11. A memory controller as recited in claim 3, wherein the controller is further to:

re-map the processor reset vector to an additional processor start vector after returning the initialization vector to the processor; and

return, in response to any other read request corresponding to the processor reset vector from another processor, the additional processor start vector.

12. A memory controller as recited in claim 11, wherein the initialization vector is an address within the code initialization process and wherein the additional processor start vector and the initialization vector are different addresses within the code initialization process.

13. A memory controller as recited in claim 3, wherein the controller is to reset the processor by clearing a state of the processor.

14. A memory controller as recited in claim 13, wherein the clearing the state of the processor comprises clearing all instructions and data from any caches or buffers of the processor.

15. A memory controller as recited in claim 3, wherein the controller is to reset the processor by asserting, on a processor bus, a reset signal to the processor.

16. A memory controller as recited in claim 15, wherein the reset signal comprises RESET#.

17. A method comprising;

allowing a computer to begin operation based on untrustworthy code;

loading, under the control of the untrustworthy code, additional code into memory;

initiating execution of the additional code in a secure manner despite the untrustworthy code in the computer;

mapping a central processing unit reset vector to an initialization vector;

receiving a read request corresponding to the central processing unit reset vector from one central processing unit;

returning, in response to the read request, the initialization vector to the one central processing unit; and

allowing the one central processing unit to access the memory beginning with the initialization vector.

18. A method as recited in claim 17, wherein the initiating further comprises initiating execution of the additional code in a secure manner despite both the untrustworthy code in the computer and other pre-existent state of the computer.

19. A method as recited in claim 17, wherein the initiating execution of the additional code in a secure manner comprises:

preventing each of one or more central processing units in the computer from accessing the memory;

preventing each of one or more bus masters in the computer from accessing the memory;

resetting each of the one or more central processing units;

allowing the one central processing unit to access the memory and execute a code initialization process; and

after execution of the code initialization process, allowing any other central processing units and any of the one or more bus masters to access the memory.

20. A method as recited in claim 17, wherein the initiating comprises initiating execution of the additional code in a secure manner without requiring any additional bus transactions to be supported by a processor in the computer.

21. A method as recited in claim 17, further comprising:

re-mapping the central processing unit reset vector to an additional central processing unit start vector after returning the initialization vector to the one central processing unit; and

returning, in response to any other read request corresponding to the central processing unit reset vector from another central processing unit, the additional central processing unit start vector.

22. A method as recited in claim 17, wherein the loading the additional code comprises copying different portions of the additional code from a plurality of different sources including one or more of:

a local mass storage device, a remote device, and a local chipset.

23. A method comprising:

booting, based on untrustworthy code, a computer;

loading a trusted core into memory; and

initiating secure execution of the trusted core by;

mapping a central processing unit reset vector to an initialization vector;

resetting each of one or more central processing units in the computer;

receiving, after the mapping and the resetting, a read request corresponding to the central processing unit reset vector from one of the one or more central processing units;

returning, in response to the read request, the initialization vector to the one central processing unit; and

allowing the one central processing unit to access the memory beginning with the initialization vector.

24. A method as recited in claim 23, wherein the initialization vector is an address within the trusted core in the memory.

25. A method as recited in claim 23, further comprising:

re-mapping the central processing unit reset vector to an additional central processing unit start vector after returning the initialization vector to the one central processing unit; and

returning, in response to any other read request corresponding to the central processing unit reset vector from another of the one or more central processing units, the additional central processing unit start vector.

26. A method as recited in claim 25, wherein the initialization vector is an address within the trusted core in the memory and wherein the additional central processing unit start vector and the initialization vector are different addresses within the trusted core in the memory.

27. One or more computer-readable media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:

allowing operation of the computer to begin based on untrusted code;

loading, under control of the untrusted code, a trusted core into memory;

preventing each of one or more central processing units and each of one or more bus masters in the computer from accessing the memory;

resetting each of the one or more central processing units;

allowing one central processing unit to access the memory and execute trusted core initialization code to initialize the trusted core;

after execution of the trusted core has been initialized, allowing any other central processing units and any bus masters in the computer to access the memory;

wherein the plurality of instructions further cause the one or more processors to perform acts including;

mapping a central processing unit reset vector to an initialization vector;

receiving a read request corresponding to the central processing unit reset vector from the one central processing unit;

returning, in response to the read request, the initialization vector to the one central processing unit; and

allowing the one central processing unit to access the memory beginning with the initialization vector.

28. One or more computer-readable media as recited in claim 27, wherein the one or more processors comprise one or more controllers of one or more memory controllers.

29. One or more computer-readable media as recited in claim 28, wherein the one or more memory controllers are distributed among the one or more central processing units.

30. One or more computer-readable media as recited in claim 28, wherein the plurality of instructions comprise microcode to be executed by the one or more memory controllers.

31. One or more computer-readable media as recited in claim 27, wherein the untrusted code includes code from a basic input output system (BIOS) and code from a plurality of option read only memories (ROMs).

32. One or more computer-readable media as recited in claim 27, wherein the preventing comprises preventing each of the one or more central processing units and each of the one or more bus masters from accessing the memory in response to an initialize trusted core command received from one of the one or more central processing units.

33. One or more computer-readable media as recited in claim 27, wherein the loading the trusted core comprises copying different portions of the trusted core from a plurality of different sources.

34. One or more computer-readable media as recited in claim 27, wherein the loading the trusted core comprises copying different parts of the trusted core from one or more sources and combining the different parts to assemble the trusted core.

35. One or more computer-readable media as recited in claim 34, wherein combining the different parts comprises exclusive-ORing bits of the different parts.

36. One or more computer-readable media as recited in claim 27, wherein the loading the trusted core comprises copying at least a portion of the trusted core from a local mass storage device into the memory.

37. One or more computer-readable media as recited in claim 27, wherein the loading the trusted core comprises copying at least a portion of the trusted core from a remote device into the memory.

38. One or more computer-readable media as recited in claim 27, wherein the loading the trusted core comprises copying at least a portion of the trusted core from a chip of the computer.

39. One or more computer-readable media as recited in claim 27, wherein the preventing comprises ignoring all requests for access to the memory from the one or more central processing units and one or more bus masters.

40. One or more computer-readable media as recited in claim 27, wherein the plurality of instructions further cause the one or more processors to perform acts including:

extracting a cryptographic measure of the trusted core in the memory; and

storing the extracted cryptographic measure.

41. One or more computer-readable media as recited in claim 40, wherein the plurality of instructions further cause the one or more processors to perform acts including:

resetting a cryptographic processor;

requesting the cryptographic processor to extract the cryptographic measure; and

receiving the extracted cryptographic measure from the cryptographic processor.

42. One or more computer-readable media as recited in claim 27, wherein the resetting each of the one or more central processing units comprises asserting a processor bus reset signal to each of the one or more central processing units.

43. One or more computer-readable media as recited in claim 27, wherein the initialization vector is an address within the trusted core in the memory.

44. One or more computer-readable media as recited in claim 27, wherein the plurality of instructions further cause the one or more processors to perform acts including:

re-mapping the central processing unit reset vector to an additional central processing unit start vector after returning the initialization vector to the one central processing unit; and

returning, in response to any other read request corresponding to the central processing unit reset vector from another central processing unit, the additional central processing unit start vector.

45. One or more computer-readable media as recited in claim 44, wherein the initialization vector is an address within the trusted core in the memory and wherein the additional central processing unit start vector and the initialization vector are different addresses within the trusted core in the memory.

46. One or more computer-readable media as recited in claim 44, wherein both the initialization vector and the additional central processing unit start vector are obtained from the trusted core.

49. One or more computer-readable media as recited in claim 27, wherein the resetting comprises clearing a state of each of the one or more central processing units.

50. One or more computer-readable media as recited in claim 49, wherein the state of a central processing unit comprises instructions and data residing in any caches and buffers of the central processing unit.

51. One or more computer-readable media as recited in claim 49, wherein the state of a central processing unit comprises instructions and data residing in any registers of the central processing unit.