Method for verifying functional integrity of computer hardware, particularly data storage devices

• US 6,938,188 B1
• Filed: 01/29/2002
• Issued: 08/30/2005
• Est. Priority Date: 01/29/2002
• Status: Active Grant

• Current Assignee: Quantum Corporation (Chi Ko Investment Co., Ltd.)
• Original Assignee: Advanced Digital Information Corporation (Chi Ko Investment Co., Ltd.)
• Inventors: Kelleher, Terence M.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Wilson, Yolanda L
• Application Number:
  US10/058,243
• Time in Patent Office: 1,309 Days
• Field of Search: 714/5, 714/6, 714/43, 714/42, 714/56, 714/750
• US Class Current: 714/43
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults

Abstract

The present invention features a method for performing an end-to-end data path integrity check in a computer or computer-like system such as a storage router. A predetermined data test pattern is stored in a memory and then transmitted across a data path by a data initiator to a data receiver. The received data test pattern is then retransmitted to the data initiator where it is compared to the original data. Any discrepancies cause an error condition to be declared. The data path may be disabled until the defective component in the data path is isolated and fixed. The method is hardware independent so it may be easily used in an open systems environment where hardware components may be provided by different vendors.

Claims

1. In a computing network having at least two data storage or processing devices, a method performed by a computer system for providing a complete end-to-end data path verification in the computer system, the computer system comprising at least a first physical data path and a second physical data path from a processor of the computer system to a data receiver of the computer system, the method comprising:

providing a data initiator within the computer system, the data initiator comprising the processor, wherein the processor is coupled to the first and second physical data paths, and wherein the first and second physical data paths within the computer system are configured to be coupled to the at least two data storage or processing devices in the computing network and external to the computer system;

transmitting a predetermined data test pattern from the processor to the data receiver of the computer system over the first physical data path, wherein the first physical data path is within the computer system;

requesting from the data receiver the transmitted predetermined data test pattern that the data receiver received from the data initiator;

reading the received data test pattern from the data receiver over the second physical data path, wherein the second physical path is within the computer system; and

comparing the predetermined data test pattern transmitted to the data receiver over the first physical data path with the data test pattern read from the data receiver over the second physical data path.

2. The method for providing a complete end-to-end data path verification in a computer system having at least a first physical data path and a second physical data path, as recited in claim 1, the method further comprising:

indicating an error condition when the predetermined data pattern transmitted to the data receiver over the first physical data path and the data test pattern read from the data receiver over the second physical data path are different.

3. The method for providing a complete end-to-end data path verification in a computer system having at least a first physical data path and a second physical data path, as recited in claim 2, wherein the transmitting, requesting, reading, and comparing are repeated periodically.

4. The method for providing a complete end-to-end data path verification in a computer system having at least a first physical data path and a second physical data path, as recited in claim 2, wherein the data receiver comprises at least one of the devices:

a SCSI controller, a memory controller, a fibre channel controller.

5. The method for providing a complete end-to-end data path verification in a computer system having at least a first physical data path and a second physical data path, as recited in claim 1, wherein the computer system comprises one of the group:

a computer and storage router.

6. The method for providing a complete end-to-end data path verification in a computer system having at least a first physical data path and a second physical data path, as recited in claim 5, wherein the computer system further comprises a PCI bus and PCI bridge.

7. The method for providing a complete end-to-end data path verification in a computer system having at least a first physical data path and a second physical data path, as recited in claim 6, wherein the complete end-to-end data path comprises a physical connection with a memory controller.

8. A data storage router having at least two physical data paths for providing a complete end-to-end data path verification in a computer network, the at least two physical data paths comprising a first data path and a second data path, the computer network comprising the storage router and at least two data storage or processing devices, the data storage router coupled to the at least two data storage or processing devices, the data storage router comprising:

a processor that creates a data test pattern, the data test pattern created to exercise all data lines in the first and second data paths in a high state and a low state;

a buffer memory for storing a data test pattern;

a first data path for transferring within the data storage router the data test pattern from the processor to the memory within the data storage router;

a second data path within the data storage router from the processor to the memory within the data storage router for verifying the transferred data test pattern; and

wherein the first and second data paths are configured to be able to be coupled to the at least two data storage or processing devices external to the data storage router.

9. The data storage router of claim 8 wherein a memory controller is operatively coupled to the first and second data paths.

10. The data storage router of claim 9 wherein the first path includes a physical coupling between the processor and the memory controller and the second data path includes a PCI bus to which the processor and memory controller are operatively coupled.

11. The data storage router of claim 9 wherein the first data path includes a PCI bus to which the processor and memory controller are coupled and the second data path includes a physical coupling between the processor and the memory controller.

12. The data storage router of claim 8 wherein the first data path includes a first PCI bus and the second data path includes a second PCI bus.

13. The data storage router of claim 8 wherein the processor transfers the data test pattern periodically.

14. The data storage router of claim 8 wherein the processor transfers the data test pattern when a host performs an ending action.

15. The data storage router of claim 8 wherein the data test pattern is separately transferred and verified using both physical data paths.