Method for performing statistical post processing in semiconductor manufacturing using ID cells
First Claim
Patent Images
1. A method for manufacturing a semiconductor integrated circuit, the method comprising:
- providing a wafer having a plurality of integrated circuit dies;
using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; and
monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell.
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Abstract
A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated circuit to monitor an operating parameter for the circuit and to determine a unique identifier for the die. The parameter is analyzed in post processing.
43 Citations
24 Claims
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1. A method for manufacturing a semiconductor integrated circuit, the method comprising:
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providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; and monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit test fixture configured for interconnection between a semiconductor tester and a wafer, comprising:
a plurality of probe tips configured to provide electrical contact with a corresponding plurality of pads on a semiconductor wafer, wherein a first group of the plurality of pads comprises pads connected to an identification cell located within an integrated circuit die on the wafer and a second group of the plurality of pads is connected to an electrical testing structure located in a scribe line adjacent to the die. - View Dependent Claims (10, 11, 12)
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13. The integrated circuit test fixture as recited in clam 9 wherein the plurality of probe tips are connected to a printed circuit board of the test fixture, the printed circuit board configured for electrical connection to a tester.
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14. A method of manufacturing a semiconductor integrated circuit, the method comprising:
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providing a wafer having a plurality of dies; generating an identification number from an identification cell located on each of the plurality of dies; monitoring the identification number before separating the plurality of dies from the wafer by using a generic interface configured to access pads on a plurality of different integrated circuit designs; and using the monitored identification number in a statistical post processing to identify defects in any of the plurality of dies. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method for manufacturing a semiconductor integrated circuit, the method comprising:
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providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; and monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fire to provide contact with contacts on the wafer corresponding to the identification cell wherein the contacts are electrically connected to the identification cell and positioned in a predetermined standardized geometric location relative to the electrical testing structures located in the scribe line.
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22. A method for manufacturing a semiconductor integrated circuit, the method comprising:
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providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell; and using the test fixture to access a contact on at least one of the plurality of integrated circuit dies to measure a performance parameter wherein the performance parameter at least one of a supply current, a supply voltage, and a quiescent current.
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23. A method for manufacturing a semiconductor integrated circuit, the method comprising:
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providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell thereby providing a unique identification number for the cell; and storing the identification number along with location data indicating the location of the first of the plurality of integrated circuit dies on the wafer. - View Dependent Claims (24)
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Specification