Semiconductor device and a method of fabricating the same

• US 6,939,776 B2
• Filed: 11/19/2001
• Issued: 09/06/2005
• Est. Priority Date: 09/29/1998
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Saito, Hiroaki, Onda, Masahito, Kubo, Hirotoshi, Kitagawa, Masanao, Kuwako, Eiichiroh
• Primary Examiner(s): Thompson, Craig A.
• Assistant Examiner(s): Harrison, Monica D.
• Application Number:
  US09/988,272
• Publication Number:
  US 20020030233A1
• Time in Patent Office: 1,387 Days
• Field of Search: 438/450, 438/449, 438/447, 438/444, 438/443, 438/433, 438/424, 438/420, 438/400, 438/249, 438/135, 438/138, 438/268, 438/269, 438/270, 438/271, 438/272, 438/273, 438/274, 438/197, 438/301, 438/303, 438/306, 438/689, 257/402, 257/368, 257/330
• US Class Current: 438/400
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 which is exposed through the recess, the side wall insulator 28, and the insulating film.

Claims

1. A method of fabricating a semiconductor device, comprising the steps of:

forming a drain layer of a first conduction type on a surface of a semiconductor substrate of the first conduction type;

forming a first insulating film on said drain layer;

forming a first conductive layer on said first insulating film;

forming a second insulating film on said first conductive layer;

patterning said second insulating film, said first conductive layer, and said first insulating film, to form a gate insulating film from said first insulating film, and a gate electrode from said first conductive layer;

implanting an impurity of a second conduction type opposite to the first conduction type into a surface of said drain layer using a gate electrode as a mask, thereby forming a channel region of the second conductive type;

implanting an impurity of the first conduction type into said channel region using said gate electrode as a mask, thereby forming an impurity region of the first conduction type;

forming a third insulating film of one layer so as to cover a surface of the impurity region, said walls of said gate insulating film, said gate electrode, and said second insulating film, and an upper face of said second insulating film;

etching back said third insulating film to form a side wall insulator of said third insulating film, by maintaining said third insulating film selectively on side walls of said gate insulating film, said gate electrode, and said second insulating film and at the same time form a recess so as to penetrate the impurity region, thereby forming a source region of the impurity region; and

forming a second conductive layer on an entire surface, and patterning said second conductive layer, thereby forming a wiring layer.

2. The method of fabricating a semiconductor device, according to the claim 1, further comprising a step of:

introducing an impurity of the second conduction type into the bottom of the recess to form a body contact region of the second conduction type after etching the impurity region prior to forming a second conductive layer.

3. The method of fabricating a semiconductor device, according to the claim 1, further comprising the steps of:

forming a fourth thick insulating layer on a surface of the semiconductor substrate; and

patterning the fourth thick insulation layer so as to remain a peripheral region of the substrate, prior to forming the drain region.

4. The method of fabricating a semiconductor device according to claim 1, wherein an upper surface and a side surface of the source region are directly contacted with the wiring layer.

5. The method of fabricating a semiconductor device according to claim 1, wherein the third insulating film is formed in one step.

6. A method of fabricating a semiconductor device, comprising the steps of:

forming a drain layer of a first conduction type on a surface of a semiconductor substrate of the first conduction type;

forming a first insulating film on said drain layer;

forming a first conductive layer on said first insulating film;

forming a second insulating film on said first conductive layer;

patterning said second insulating film, said first conductive layer, and said first insulating film, to form a gate insulating film from said first insulating film, and a gate electrode from said first conductive layer;

implanting an impurity of a second conduction type opposite to the first conduction type into a surface of said drain layer using a gate electrode as a mask, thereby forming a channel region of the second conductive type;

implanting an impurity of the first conduction type into said channel region using said gate electrode as a mask, thereby forming an impurity region of the first conduction type;

forming a third insulating film of one layer so as to cover a surface of the impurity region, said walls of said gate insulating film, said gate electrode, and said second insulating film, and an upper face of said second insulating film;

forming a mask pattern having an opening located in a center of the impurity region and covering an entire surface except for the opening before etching the impurity region;

etching the impurity region by using the mask pattern to form a recess deeper than the impurity region, thereby forming a source region of the impurity region remaining;

introducing an impurity of the second conduction type into the bottom of the recess to form a body contact region of the second conduction type;

then etching back said third insulating film to form a side wall insulator of said third insulating film, by maintaining said third insulating film selectively on side walls of said gate insulating film, said gate electrode, and said second insulating film; and

forming a second conductive layer on an entire surface, and patterning said second conductive layer, thereby forming a wiring layer.

7. The method of fabricating a semiconductor device according to claim 6, wherein the opening of the mask pattern is formed smaller than a region of the impurity region between the adjacent sidewall insulators.

8. A method of fabricating a semiconductor device, comprising the steps of:

forming a drain layer of a first conduction type on a surface of a semiconductor substrate of the first conduction type;

forming a first insulating film on said drain layer;

forming a first conductive layer on said first insulating film;

forming a second insulating film on said first conductive layer;

patterning said second insulating film, said first conductive layer, and said first insulating film, to form a gate insulating film from said first insulating film, and a gate electrode from said first conductive layer;

implanting an impurity of a second conduction type opposite to the first conduction type into a surface of said drain layer using a gate electrode as a mask, thereby forming a channel region of the second conductive type;

implanting an impurity of the first conduction type into said channel region using said gate electrode as a mask, thereby forming an impurity region of the first conduction type;

forming a third insulating film of one layer so as to cover a surface of the impurity region, said walls of said gate insulating film, said gate electrode, and said second insulating film, and an upper face of said second insulating film;

etching back said third insulating film to form a side wall insulator of said third insulating film, by maintaining said third insulating film selectively on side walls of said gate insulating film, said gate electrode, and said second insulating film and form a recess of which a side wall is flush with a side wall of the side wall insulator and which is penetrating the impurity region, thereby forming a source region of the impurity region; and

forming a second conductive layer on an entire surface, and patterning said second conductive layer, thereby forming a wiring layer.