Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate

• US 6,939,781 B2
• Filed: 06/27/2003
• Issued: 09/06/2005
• Est. Priority Date: 06/27/2003
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Redd, Randy D., Fisher, Paul A., Hartin, Olin L., Klingbeil, Lawrence S., Lan, Ellen, Li, Hsin-Hua P., Weitzel, Charles E.
• Primary Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/609,106
• Publication Number:
  US 20040262629A1
• Time in Patent Office: 802 Days
• Field of Search: 438/182, 438/270, 438/294, 438/299, 438/454, 438/586, 438/589
• US Class Current: 438/454
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66871 Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.

Claims

1. A method of manufacturing a semiconductor component, the method comprising:

providing a semiconductor substrate;

forming a first dielectric layer above the semiconductor substrate;

forming a field plate above the first dielectric layer;

self-aligning a gate electrode to the field plate; and

forming a first ohmic contact region and a second ohmic contact region above the semiconductor substrate,

wherein;

self-aligning the gate electrode to the field plate further comprises;

forming the gate electrode after forming the first ohmic contact region and the second ohmic contact region; and

forming the gate electrode to be between the first ohmic contact region and the second ohmic contact region.

2. The method of claim 1 further comprising:

forming a semiconductor layer above the semiconductor substrate before forming the first dielectric layer,

wherein;

forming the first dielectric layer comprises;

forming the first dielectric layer above the semiconductor layer.

3. The method of claim 1 wherein:

self aligning the gate electrode to the field plate further comprises;

forming a second dielectric layer above the field plate and the first dielectric layer;

forming a hole through the second dielectric layer to expose a portion of the field plate;

removing the portion of the field plate;

removing a portion of the first dielectric layer;

depositing a third dielectric layer over the second dielectric layer and in the hole;

etching the third dielectric layer to form a spacer inside the hole; and

forming the gate electrode in the hole.

4. The method of claim 1 wherein:

forming the gate electrode further comprises;

forming the gate electrode to be separated from the field plate by a distance of between approximately 20 and 400 nanometers.

5. The method of claim 1 wherein:

self-aligning the gate electrode comprises;

shortening a length of the field plate to between approximately 300 and 2000 nanometers.

6. The method of claim 1 wherein:

forming the field plate comprises;

forming the field plate to comprise titanium tungsten nitride.

7. A method of manufacturing a semiconductor component, the method comprising:

providing a semiconductor substrate;

forming a first dielectric layer above the semiconductor substrate;

forming a field plate above the first dielectric layer;

self-aligning a gate electrode to the field plate;

forming a semiconductor layer above the semiconductor substrate before forming the first dielectric layer; and

forming a gate recess in the semiconductor layer,

wherein;

forming the first dielectric layer comprises;

forming the first dielectric layer above the semiconductor layer.

8. A method of manufacturing a semiconductor component, the method comprising:

providing a semiconductor substrate;

forming a first dielectric layer above the semiconductor substrate;

forming a field plate above the first dielectric layer; and

self-aligning a gate electrode to the field plate,

wherein;

self aligning the gate electrode to the field plate further comprises;

forming a second dielectric layer above the field plate and the first dielectric layer;

forming a hole through the second dielectric layer to expose a portion of the field plate;

removing the portion of the field plate;

removing a portion of the first dielectric layer;

depositing a third dielectric layer over the second dielectric layer and in the hole;

etching the third dielectric layer to form a spacer inside the hole; and

forming the gate electrode in the hole; and

forming the second dielectric layer comprises;

forming the second dielectric layer to comprise;

a first tetra-ethyl-ortho-silicate layer;

an aluminum-nitride layer; and

a second tetra-ethyl-ortho-silicate layer.

9. The method of claim 8 wherein:

forming the second dielectric layer further comprises;

forming the aluminum-nitride layer between the first tetra-ethyl-ortho-silicate layer and the second tetra-ethyl-ortho-silicate layer.

10. The method of claim 8 wherein:

forming the gate electrode comprises;

forming a T-gate electrode having a titanium tungsten nitride layer.

11. The method of claim 10 wherein:

forming the T-gate electrode further comprises;

plating a gold layer above the titanium tungsten nitride layer.

12. A method of manufacturing a semiconductor component, the method comprising:

providing a semiconductor substrate;

forming a first dielectric layer above the semiconductor substrate;

forming a field plate above the first dielectric layer; and

self-aligning a gate electrode to the field plate,

wherein;

forming the first dielectric layer comprises;

forming the first dielectric layer to comprise;

a silicon-nitride layer; and

an aluminum-nitride layer.

13. A method of manufacturing a semiconductor component, the method

comprising:

providing a semiconductor substrate;

forming a first dielectric layer above the semiconductor substrate;

forming a field plate comprising titanium tungsten nitride above the first dielectric layer;

simultaneously forming a first ohmic contact region and a second ohmic contact region above the semiconductor substrate;

forming a second dielectric layer above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region;

forming a hole in the second dielectric layer and between the first ohmic contact region and the second ohmic contact region to expose a portion of the field plate;

removing the portion of the field plate;

removing a portion of the first dielectric layer;

depositing a third dielectric layer over the second dielectric layer and in the hole;

etching the third dielectric layer to form a spacer inside the hole; and

forming a T-gate electrode in and over the hole;

wherein;

the spacer isolates the field plate from the T-gate electrode.

14. The method of claim 13 further comprising:

providing a semiconductor layer above the semiconductor substrate and below the first dielectric layer; and

forming a gate recess in the semiconductor layer,

wherein;

forming the T-gate electrode comprises;

forming the T-gate electrode in the hole and in the gate recess.

15. The method of claim 13 wherein:

forming the T-gate electrode further comprises;

forming the T-gate electrode to be separated from the field plate by a distance of between approximately 20 and 400 nanometers.

16. The method of claim 13 wherein:

forming the field plate comprises;

forming the field plate to have a length of between approximately 300 and 2000 nanometers.

17. The method of claim 13 wherein:

forming the second dielectric layer, forming the hole, removing the portion of the field plate, removing the portion of the first dielectric layer, depositing the third dielectric layer, etching the third dielectric layer, and forming the T-gate electrode comprise self-aligning the T-gate electrode to the field plate.